[PATCH v2 1/3] riscv: timer: Update the sifive clint timer driver to support aclint

[Rick Chen]

> From: Bin Meng <bmeng at tinylab.org>
> Sent: Wednesday, June 21, 2023 11:12 PM
> To: u-boot at lists.denx.de
> Cc: Anup Patel <anup at brainfault.org>; Atish Patra <atishp at atishpatra.org>; Bin Meng <bmeng.cn at gmail.com>; Palmer Dabbelt <palmer at dabbelt.com>; Paul Walmsley <paul.walmsley at sifive.com>; Rick Jian-Zhi Chen(陳建志) <rick at andestech.com>
> Subject: [PATCH v2 1/3] riscv: timer: Update the sifive clint timer driver to support aclint
>
> This RISC-V ACLINT specification [1] defines a set of memory mapped devices which provide inter-processor interrupts (IPI) and timer functionalities for each HART on a multi-HART RISC-V platform.
>
> The RISC-V ACLINT specification is defined to be backward compatible with the SiFive CLINT specification, however the device tree binding is a new one. This change updates the sifive clint timer driver to support ACLINT mtimer device, using a per-driver data field to hold the mtimer offset to the base address encoded in the mtimer node.
>
> [1] https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc
>
> Signed-off-by: Bin Meng <bmeng at tinylab.org>
>
> ---
>
> Changes in v2:
> - drop ae350.h changes
>
>  drivers/timer/sifive_clint_timer.c     | 16 +++++++++++-----
>  include/configs/qemu-riscv.h           |  2 +-
>  include/configs/sifive-unleashed.h     |  2 +-
>  include/configs/starfive-visionfive2.h |  1 +
>  4 files changed, 14 insertions(+), 7 deletions(-)

Reviewed-by: Rick Chen <rick at andestech.com>