[PATCH] riscv: Fix alignment of RELA sections in the linker scripts

[Rick Chen]

> From: Bin Meng <bmeng at tinylab.org>
> Sent: Wednesday, June 21, 2023 11:07 PM
> To: u-boot at lists.denx.de
> Cc: Andrew Scull <ascull at google.com>; Leo Yu-Chi Liang(梁育齊) <ycliang at andestech.com>; Rick Jian-Zhi Chen(陳建志) <rick at andestech.com>; Simon Glass <sjg at chromium.org>
> Subject: [PATCH] riscv: Fix alignment of RELA sections in the linker scripts
>
> In current linker script both .efi_runtime_rel and .rela.dyn sections are of RELA type whose entry size is either 12 (RV32) or 24 (RV64).
> These two are arranged as an continuous region on purpose so that the prelink-riscv executable can fix up the PIE addresses in one loop.
>
> However there is an 'ALIGN(8)' between these 2 sections which might cause a gap to be inserted between thesse 2 sections to satify the alignment requirement on RV32. This would break the assumption of the prelink process and generate an unbootable image.
>
> Fixes: 9a6569a043d3 ("riscv: Update alignment for some sections in linker scripts")
> Signed-off-by: Bin Meng <bmeng at tinylab.org>
>
> ---
> This fix should go into the v2023.07 release.
>
>  arch/riscv/cpu/u-boot.lds | 4 +---
>  1 file changed, 1 insertion(+), 3 deletions(-)

Reviewed-by: Rick Chen <rick at andestech.com>

Hi Leo,

Please help to push this patch ASAP.

Thanks,
Rick