[RFC PATCH] riscv: sifive: fu70: downclock CPU clock for stability

[Icenowy Zheng]

When building the package `rustc` for AOSC OS on HiFive Unmatched,
random SIGSEGV prevents the package from getting correctly built.
Downclocking the CPU PLL clock seems to allow rustc to be built,
although taking much more time.

Downclock the CPU PLL frequency for stability.

Signed-off-by: Icenowy Zheng <uwu at icenowy.me>
---
 arch/riscv/dts/fu740-c000-u-boot.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/riscv/dts/fu740-c000-u-boot.dtsi b/arch/riscv/dts/fu740-c000-u-boot.dtsi
index 706224b384..6b80cab588 100644
--- a/arch/riscv/dts/fu740-c000-u-boot.dtsi
+++ b/arch/riscv/dts/fu740-c000-u-boot.dtsi
@@ -8,7 +8,7 @@
 / {
 	cpus {
 		assigned-clocks = <&prci FU740_PRCI_CLK_COREPLL>;
-		assigned-clock-rates = <1200000000>;
+		assigned-clock-rates = <988000000>;
 		bootph-pre-ram;
 		cpu0: cpu at 0 {
 			clocks = <&prci FU740_PRCI_CLK_COREPLL>;
-- 
2.39.1