[PATCH] rockchip: sdhci: rk3568: fix clock setting logic

[Vasily Khoruzhick]

mmc->tran_speed is max clock, but currently rk3568_sdhci_set_ios_post
uses it if its != 0, regardless of mmc->clock value, and it breaks
eMMC controller.

Without this patch 'mmc dev 0; mmc dev 1; mmc dev 0' is enough for
breaking eMMC, since first initialization sets mmc->mmc_tran speed
to non-zero value (26MHz in my case), and on subsequent re-init when
mmc layer asks for 400KHz it sets 26MHz instead.

Fix it by using MAX(mmc->tran_speed, mmc->clock)

Signed-off-by: Vasily Khoruzhick <anarsoul at gmail.com>
---
 drivers/mmc/rockchip_sdhci.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc/rockchip_sdhci.c
index 9608770d4e..1ac95f32b3 100644
--- a/drivers/mmc/rockchip_sdhci.c
+++ b/drivers/mmc/rockchip_sdhci.c
@@ -394,11 +394,11 @@ static int rk3568_sdhci_set_enhanced_strobe(struct sdhci_host *host)
 static int rk3568_sdhci_set_ios_post(struct sdhci_host *host)
 {
 	struct mmc *mmc = host->mmc;
-	uint clock = mmc->tran_speed;
+	uint clock = mmc->clock;
 	u32 reg, vendor_reg;
 
-	if (!clock)
-		clock = mmc->clock;
+	if (mmc->tran_speed && mmc->clock > mmc->tran_speed)
+		clock = mmc->tran_speed;
 
 	rk3568_sdhci_emmc_set_clock(host, clock);
 
-- 
2.39.2