[PATCH 13/13] x86: Add on to existing MTRRs in SPL

[Simon Glass]

We don't actually set up all of these registers in SPL, so using
mtrr_commit() with erase some. Use mtrr_set_next_var() instead.

Signed-off-by: Simon Glass <sjg at chromium.org>
---

 arch/x86/lib/spl.c                  | 10 +++++-----
 configs/chromebook_link64_defconfig |  2 ++
 2 files changed, 7 insertions(+), 5 deletions(-)

diff --git a/arch/x86/lib/spl.c b/arch/x86/lib/spl.c
index 0f2319ccc212..88d7e1424174 100644
--- a/arch/x86/lib/spl.c
+++ b/arch/x86/lib/spl.c
@@ -147,14 +147,14 @@ static int x86_spl_init(void)
 	}
 
 	/* Cache the SPI flash. Otherwise copying the code to RAM takes ages */
-	ret = mtrr_add_request(MTRR_TYPE_WRBACK,
+	mtrr_set_next_var(MTRR_TYPE_WRBACK,
 			       (1ULL << 32) - CONFIG_XIP_ROM_SIZE,
 			       CONFIG_XIP_ROM_SIZE);
-	if (ret) {
-		debug("%s: SPI cache setup failed (err=%d)\n", __func__, ret);
-		return ret;
+	if (_LOG_DEBUG) {
+		ret = mtrr_list(mtrr_get_var_count(), MP_SELECT_BSP);
+		if (ret)
+			printf("mtrr_list failed\n");
 	}
-	mtrr_commit(true);
 # else
 	ret = syscon_get_by_driver_data(X86_SYSCON_PUNIT, &punit);
 	if (ret)
diff --git a/configs/chromebook_link64_defconfig b/configs/chromebook_link64_defconfig
index 8c75d654290b..192cbbecbe0e 100644
--- a/configs/chromebook_link64_defconfig
+++ b/configs/chromebook_link64_defconfig
@@ -69,6 +69,7 @@ CONFIG_TFTP_TSIZE=y
 CONFIG_USE_ROOTPATH=y
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
+CONFIG_SPL_OF_TRANSLATE=y
 # CONFIG_ACPIGEN is not set
 CONFIG_LBA48=y
 CONFIG_SYS_64BIT_LBA=y
@@ -88,6 +89,7 @@ CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
 CONFIG_FRAMEBUFFER_VESA_MODE_11A=y
 CONFIG_VIDEO_IVYBRIDGE_IGD=y
 CONFIG_CONSOLE_SCROLL_LINES=5
+# CONFIG_SPL_USE_TINY_PRINTF is not set
 CONFIG_CMD_DHRYSTONE=y
 CONFIG_TPM=y
 # CONFIG_GZIP is not set
-- 
2.40.0.rc1.284.g88254d51c5-goog