[PATCH v2 2/7] arm: dts: rockchip: rk3288: partial sync grf and pmu nodes

Kever Yang kever.yang at rock-chips.com
Tue Mar 21 04:14:50 CET 2023


On 2023/3/16 02:33, Johan Jonker wrote:
> In order to better compare the Linux rk3288.dtsi
> version 6.3 -rc2 with the U-Boot version partial
> sync the grf and pmu nodes.
>
> Signed-off-by: Johan Jonker <jbx6244 at gmail.com>
> Reviewed-by: Simon Glass <sjg at chromium.org>
> Tested-by: Simon Glass <sjg at chromium.org>  # chromebook-jerry
Reviewed-by: Kever Yang <kever.yang at rock-chips.com>

Thanks,
- Kever
> ---
>   arch/arm/dts/rk3288.dtsi | 269 +++++++++++++++++++++++++--------------
>   1 file changed, 173 insertions(+), 96 deletions(-)
>
> diff --git a/arch/arm/dts/rk3288.dtsi b/arch/arm/dts/rk3288.dtsi
> index 9cfb86f9..f06d1f5b 100644
> --- a/arch/arm/dts/rk3288.dtsi
> +++ b/arch/arm/dts/rk3288.dtsi
> @@ -1,4 +1,4 @@
> -// SPDX-License-Identifier: GPL-2.0+
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
>
>   #include <dt-bindings/gpio/gpio.h>
>   #include <dt-bindings/interrupt-controller/irq.h>
> @@ -7,13 +7,16 @@
>   #include <dt-bindings/clock/rk3288-cru.h>
>   #include <dt-bindings/power/rk3288-power.h>
>   #include <dt-bindings/thermal/thermal.h>
> -#include <dt-bindings/video/rk3288.h>
> -#include "skeleton.dtsi"
> +#include <dt-bindings/soc/rockchip,boot-mode.h>
>
>   / {
> +	#address-cells = <1>;
> +	#size-cells = <1>;
> +
>   	compatible = "rockchip,rk3288";
>
>   	interrupt-parent = <&gic>;
> +
>   	aliases {
>   		ethernet0 = &gmac;
>   		i2c0 = &i2c0;
> @@ -732,8 +735,128 @@
>   	};
>
>   	pmu: power-management at ff730000 {
> -		compatible = "rockchip,rk3288-pmu", "syscon";
> +		compatible = "rockchip,rk3288-pmu", "syscon", "simple-mfd";
>   		reg = <0xff730000 0x100>;
> +
> +		power: power-controller {
> +			compatible = "rockchip,rk3288-power-controller";
> +			#power-domain-cells = <1>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +
> +			assigned-clocks = <&cru SCLK_EDP_24M>;
> +			assigned-clock-parents = <&xin24m>;
> +
> +			/*
> +			 * Note: Although SCLK_* are the working clocks
> +			 * of device without including on the NOC, needed for
> +			 * synchronous reset.
> +			 *
> +			 * The clocks on the which NOC:
> +			 * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
> +			 * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
> +			 * ACLK_RGA is on ACLK_RGA_NIU.
> +			 * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
> +			 *
> +			 * Which clock are device clocks:
> +			 *	clocks		devices
> +			 *	*_IEP		IEP:Image Enhancement Processor
> +			 *	*_ISP		ISP:Image Signal Processing
> +			 *	*_VIP		VIP:Video Input Processor
> +			 *	*_VOP*		VOP:Visual Output Processor
> +			 *	*_RGA		RGA
> +			 *	*_EDP*		EDP
> +			 *	*_LVDS_*	LVDS
> +			 *	*_HDMI		HDMI
> +			 *	*_MIPI_*	MIPI
> +			 */
> +			power-domain at RK3288_PD_VIO {
> +				reg = <RK3288_PD_VIO>;
> +				clocks = <&cru ACLK_IEP>,
> +					 <&cru ACLK_ISP>,
> +					 <&cru ACLK_RGA>,
> +					 <&cru ACLK_VIP>,
> +					 <&cru ACLK_VOP0>,
> +					 <&cru ACLK_VOP1>,
> +					 <&cru DCLK_VOP0>,
> +					 <&cru DCLK_VOP1>,
> +					 <&cru HCLK_IEP>,
> +					 <&cru HCLK_ISP>,
> +					 <&cru HCLK_RGA>,
> +					 <&cru HCLK_VIP>,
> +					 <&cru HCLK_VOP0>,
> +					 <&cru HCLK_VOP1>,
> +					 <&cru PCLK_EDP_CTRL>,
> +					 <&cru PCLK_HDMI_CTRL>,
> +					 <&cru PCLK_LVDS_PHY>,
> +					 <&cru PCLK_MIPI_CSI>,
> +					 <&cru PCLK_MIPI_DSI0>,
> +					 <&cru PCLK_MIPI_DSI1>,
> +					 <&cru SCLK_EDP_24M>,
> +					 <&cru SCLK_EDP>,
> +					 <&cru SCLK_ISP_JPE>,
> +					 <&cru SCLK_ISP>,
> +					 <&cru SCLK_RGA>;
> +				pm_qos = <&qos_vio0_iep>,
> +					 <&qos_vio1_vop>,
> +					 <&qos_vio1_isp_w0>,
> +					 <&qos_vio1_isp_w1>,
> +					 <&qos_vio0_vop>,
> +					 <&qos_vio0_vip>,
> +					 <&qos_vio2_rga_r>,
> +					 <&qos_vio2_rga_w>,
> +					 <&qos_vio1_isp_r>;
> +				#power-domain-cells = <0>;
> +			};
> +
> +			/*
> +			 * Note: The following 3 are HEVC(H.265) clocks,
> +			 * and on the ACLK_HEVC_NIU (NOC).
> +			 */
> +			power-domain at RK3288_PD_HEVC {
> +				reg = <RK3288_PD_HEVC>;
> +				clocks = <&cru ACLK_HEVC>,
> +					 <&cru SCLK_HEVC_CABAC>,
> +					 <&cru SCLK_HEVC_CORE>;
> +				pm_qos = <&qos_hevc_r>,
> +					 <&qos_hevc_w>;
> +				#power-domain-cells = <0>;
> +			};
> +
> +			/*
> +			 * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
> +			 * (video endecoder & decoder) clocks that on the
> +			 * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
> +			 */
> +			power-domain at RK3288_PD_VIDEO {
> +				reg = <RK3288_PD_VIDEO>;
> +				clocks = <&cru ACLK_VCODEC>,
> +					 <&cru HCLK_VCODEC>;
> +				pm_qos = <&qos_video>;
> +				#power-domain-cells = <0>;
> +			};
> +
> +			/*
> +			 * Note: ACLK_GPU is the GPU clock,
> +			 * and on the ACLK_GPU_NIU (NOC).
> +			 */
> +			power-domain at RK3288_PD_GPU {
> +				reg = <RK3288_PD_GPU>;
> +				clocks = <&cru ACLK_GPU>;
> +				pm_qos = <&qos_gpu_r>,
> +					 <&qos_gpu_w>;
> +				#power-domain-cells = <0>;
> +			};
> +		};
> +
> +		reboot-mode {
> +			compatible = "syscon-reboot-mode";
> +			offset = <0x94>;
> +			mode-normal = <BOOT_NORMAL>;
> +			mode-recovery = <BOOT_RECOVERY>;
> +			mode-bootloader = <BOOT_FASTBOOT>;
> +			mode-loader = <BOOT_BL_DOWNLOAD>;
> +		};
>   	};
>
>   	sgrf: syscon at ff740000 {
> @@ -760,13 +883,58 @@
>   	};
>
>   	grf: syscon at ff770000 {
> -		compatible = "rockchip,rk3288-grf", "syscon";
> +		compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd";
>   		reg = <0xff770000 0x1000>;
>
> +		edp_phy: edp-phy {
> +			compatible = "rockchip,rk3288-dp-phy";
> +			clocks = <&cru SCLK_EDP_24M>;
> +			clock-names = "24m";
> +			#phy-cells = <0>;
> +			status = "disabled";
> +		};
> +
>   		io_domains: io-domains {
>   			compatible = "rockchip,rk3288-io-voltage-domain";
>   			status = "disabled";
>   		};
> +
> +		usbphy: usbphy {
> +			compatible = "rockchip,rk3288-usb-phy";
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			status = "disabled";
> +
> +			usbphy0: usb-phy at 320 {
> +				#phy-cells = <0>;
> +				reg = <0x320>;
> +				clocks = <&cru SCLK_OTGPHY0>;
> +				clock-names = "phyclk";
> +				#clock-cells = <0>;
> +				resets = <&cru SRST_USBOTG_PHY>;
> +				reset-names = "phy-reset";
> +			};
> +
> +			usbphy1: usb-phy at 334 {
> +				#phy-cells = <0>;
> +				reg = <0x334>;
> +				clocks = <&cru SCLK_OTGPHY1>;
> +				clock-names = "phyclk";
> +				#clock-cells = <0>;
> +				resets = <&cru SRST_USBHOST0_PHY>;
> +				reset-names = "phy-reset";
> +			};
> +
> +			usbphy2: usb-phy at 348 {
> +				#phy-cells = <0>;
> +				reg = <0x348>;
> +				clocks = <&cru SCLK_OTGPHY2>;
> +				clock-names = "phyclk";
> +				#clock-cells = <0>;
> +				resets = <&cru SRST_USBHOST1_PHY>;
> +				reset-names = "phy-reset";
> +			};
> +		};
>   	};
>
>   	wdt: watchdog at ff800000 {
> @@ -1246,39 +1414,6 @@
>   		interrupts = <GIC_PPI 9 0xf04>;
>   	};
>
> -	cpuidle: cpuidle {
> -		compatible = "rockchip,rk3288-cpuidle";
> -	};
> -
> -	usbphy: phy {
> -		compatible = "rockchip,rk3288-usb-phy";
> -		rockchip,grf = <&grf>;
> -		#address-cells = <1>;
> -		#size-cells = <0>;
> -		status = "disabled";
> -
> -		usbphy0: usb-phy0 {
> -			#phy-cells = <0>;
> -			reg = <0x320>;
> -			clocks = <&cru SCLK_OTGPHY0>;
> -			clock-names = "phyclk";
> -		};
> -
> -		usbphy1: usb-phy1 {
> -			#phy-cells = <0>;
> -			reg = <0x334>;
> -			clocks = <&cru SCLK_OTGPHY1>;
> -			clock-names = "phyclk";
> -		};
> -
> -		usbphy2: usb-phy2 {
> -			#phy-cells = <0>;
> -			reg = <0x348>;
> -			clocks = <&cru SCLK_OTGPHY2>;
> -			clock-names = "phyclk";
> -		};
> -	};
> -
>   	pinctrl: pinctrl {
>   		compatible = "rockchip,rk3288-pinctrl";
>   		rockchip,grf = <&grf>;
> @@ -1865,62 +2000,4 @@
>   			};
>   		};
>   	};
> -
> -	power: power-controller {
> -		compatible = "rockchip,rk3288-power-controller";
> -		#power-domain-cells = <1>;
> -		rockchip,pmu = <&pmu>;
> -		#address-cells = <1>;
> -		#size-cells = <0>;
> -
> -		pd_gpu {
> -			reg = <RK3288_PD_GPU>;
> -			clocks = <&cru ACLK_GPU>;
> -		};
> -
> -		pd_hevc {
> -			reg = <RK3288_PD_HEVC>;
> -			clocks = <&cru ACLK_HEVC>,
> -				 <&cru SCLK_HEVC_CABAC>,
> -				 <&cru SCLK_HEVC_CORE>,
> -				 <&cru HCLK_HEVC>;
> -		};
> -
> -		pd_vio {
> -			reg = <RK3288_PD_VIO>;
> -			clocks = <&cru ACLK_IEP>,
> -				 <&cru ACLK_ISP>,
> -				 <&cru ACLK_RGA>,
> -				 <&cru ACLK_VIP>,
> -				 <&cru ACLK_VOP0>,
> -				 <&cru ACLK_VOP1>,
> -				 <&cru DCLK_VOP0>,
> -				 <&cru DCLK_VOP1>,
> -				 <&cru HCLK_IEP>,
> -				 <&cru HCLK_ISP>,
> -				 <&cru HCLK_RGA>,
> -				 <&cru HCLK_VIP>,
> -				 <&cru HCLK_VOP0>,
> -				 <&cru HCLK_VOP1>,
> -				 <&cru PCLK_EDP_CTRL>,
> -				 <&cru PCLK_HDMI_CTRL>,
> -				 <&cru PCLK_LVDS_PHY>,
> -				 <&cru PCLK_MIPI_CSI>,
> -				 <&cru PCLK_MIPI_DSI0>,
> -				 <&cru PCLK_MIPI_DSI1>,
> -				 <&cru SCLK_EDP_24M>,
> -				 <&cru SCLK_EDP>,
> -				 <&cru SCLK_HDMI_CEC>,
> -				 <&cru SCLK_HDMI_HDCP>,
> -				 <&cru SCLK_ISP_JPE>,
> -				 <&cru SCLK_ISP>,
> -				 <&cru SCLK_RGA>;
> -		};
> -
> -		pd_video {
> -			reg = <RK3288_PD_VIDEO>;
> -			clocks = <&cru ACLK_VCODEC>,
> -				 <&cru HCLK_VCODEC>;
> -		};
> -	};
>   };
> --
> 2.20.1
>


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