[PATCH 4/5] pinctrl: qcom: Add pinctrl driver for SM6115 SoC
Bhupesh Sharma
bhupesh.sharma at linaro.org
Fri Mar 24 09:04:17 CET 2023
Currently this pinctrl driver only supports debug UART
specific pin configuration.
Signed-off-by: Bhupesh Sharma <bhupesh.sharma at linaro.org>
---
arch/arm/mach-snapdragon/Makefile | 1 +
.../arm/mach-snapdragon/pinctrl-qrb4210-rb2.c | 59 +++++++++++++++++++
arch/arm/mach-snapdragon/pinctrl-snapdragon.c | 1 +
arch/arm/mach-snapdragon/pinctrl-snapdragon.h | 1 +
4 files changed, 62 insertions(+)
create mode 100644 arch/arm/mach-snapdragon/pinctrl-qrb4210-rb2.c
diff --git a/arch/arm/mach-snapdragon/Makefile b/arch/arm/mach-snapdragon/Makefile
index 23aa1a974c..4ee6a3902e 100644
--- a/arch/arm/mach-snapdragon/Makefile
+++ b/arch/arm/mach-snapdragon/Makefile
@@ -16,6 +16,7 @@ obj-y += pinctrl-snapdragon.o
obj-y += pinctrl-apq8016.o
obj-y += pinctrl-apq8096.o
obj-y += pinctrl-qcs404.o
+obj-y += pinctrl-qrb4210-rb2.o
obj-y += pinctrl-sdm845.o
obj-$(CONFIG_TARGET_QCS404EVB) += clock-qcs404.o
obj-$(CONFIG_TARGET_QCS404EVB) += sysmap-qcs404.o
diff --git a/arch/arm/mach-snapdragon/pinctrl-qrb4210-rb2.c b/arch/arm/mach-snapdragon/pinctrl-qrb4210-rb2.c
new file mode 100644
index 0000000000..a8ab67f20a
--- /dev/null
+++ b/arch/arm/mach-snapdragon/pinctrl-qrb4210-rb2.c
@@ -0,0 +1,59 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Qualcomm SM6115 pinctrl
+ *
+ * (C) Copyright 2023 Bhupesh Sharma <bhupesh.sharma at linaro.org>
+ *
+ */
+
+#include "pinctrl-snapdragon.h"
+#include <common.h>
+
+#define MAX_PIN_NAME_LEN 32
+static char pin_name[MAX_PIN_NAME_LEN] __section(".data");
+
+static const char * const msm_pinctrl_pins[] = {
+ "UFS_RESET",
+ "SDC1_RCLK",
+ "SDC1_CLK",
+ "SDC1_CMD",
+ "SDC1_DATA",
+ "SDC2_CLK",
+ "SDC2_CMD",
+ "SDC2_DATA",
+};
+
+static const struct pinctrl_function msm_pinctrl_functions[] = {
+ {"qup4", 1},
+ {"gpio", 0},
+};
+
+static const char *sm6115_get_function_name(struct udevice *dev,
+ unsigned int selector)
+{
+ return msm_pinctrl_functions[selector].name;
+}
+
+static const char *sm6115_get_pin_name(struct udevice *dev,
+ unsigned int selector)
+{
+ if (selector < 113) {
+ snprintf(pin_name, MAX_PIN_NAME_LEN, "GPIO_%u", selector);
+ return pin_name;
+ } else {
+ return msm_pinctrl_pins[selector - 113];
+ }
+}
+
+static unsigned int sm6115_get_function_mux(unsigned int selector)
+{
+ return msm_pinctrl_functions[selector].val;
+}
+
+struct msm_pinctrl_data sm6115_data = {
+ .pin_count = 120,
+ .functions_count = ARRAY_SIZE(msm_pinctrl_functions),
+ .get_function_name = sm6115_get_function_name,
+ .get_function_mux = sm6115_get_function_mux,
+ .get_pin_name = sm6115_get_pin_name,
+};
diff --git a/arch/arm/mach-snapdragon/pinctrl-snapdragon.c b/arch/arm/mach-snapdragon/pinctrl-snapdragon.c
index 826dc51486..e7efb5b29f 100644
--- a/arch/arm/mach-snapdragon/pinctrl-snapdragon.c
+++ b/arch/arm/mach-snapdragon/pinctrl-snapdragon.c
@@ -151,6 +151,7 @@ static const struct udevice_id msm_pinctrl_ids[] = {
{ .compatible = "qcom,msm8916-pinctrl", .data = (ulong)&apq8016_data },
{ .compatible = "qcom,msm8996-pinctrl", .data = (ulong)&apq8096_data },
{ .compatible = "qcom,sdm845-pinctrl", .data = (ulong)&sdm845_data },
+ { .compatible = "qcom,sm6115-pinctrl", .data = (ulong)&sm6115_data },
{ .compatible = "qcom,qcs404-pinctrl", .data = (ulong)&qcs404_data },
{ }
};
diff --git a/arch/arm/mach-snapdragon/pinctrl-snapdragon.h b/arch/arm/mach-snapdragon/pinctrl-snapdragon.h
index 178ee01a41..7f543b0f5a 100644
--- a/arch/arm/mach-snapdragon/pinctrl-snapdragon.h
+++ b/arch/arm/mach-snapdragon/pinctrl-snapdragon.h
@@ -28,6 +28,7 @@ struct pinctrl_function {
extern struct msm_pinctrl_data apq8016_data;
extern struct msm_pinctrl_data apq8096_data;
extern struct msm_pinctrl_data sdm845_data;
+extern struct msm_pinctrl_data sm6115_data;
extern struct msm_pinctrl_data qcs404_data;
#endif
--
2.38.1
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