[PATCH v3 09/16] x86: coreboot: Use a memory-mapped UART

[Simon Glass]

This is much more common on modern hardware, so default to using it.

This does not affect the normal UART, but does allow the debug UART to
work, since it uses serial_out_shift(), etc.

Signed-off-by: Simon Glass <sjg at chromium.org>
---

(no changes since v2)

Changes in v2:
- Expand commit message to explain this is for the debug UART
- Update the defconfig instead

 configs/coreboot64_defconfig | 1 -
 configs/coreboot_defconfig   | 1 -
 2 files changed, 2 deletions(-)

diff --git a/configs/coreboot64_defconfig b/configs/coreboot64_defconfig
index ec672e59e898..60a1924e9e53 100644
--- a/configs/coreboot64_defconfig
+++ b/configs/coreboot64_defconfig
@@ -62,7 +62,6 @@ CONFIG_ATAPI=y
 CONFIG_LBA48=y
 CONFIG_SYS_64BIT_LBA=y
 # CONFIG_PCI_PNP is not set
-CONFIG_SYS_NS16550_PORT_MAPPED=y
 CONFIG_SOUND=y
 CONFIG_SOUND_I8254=y
 CONFIG_CONSOLE_SCROLL_LINES=5
diff --git a/configs/coreboot_defconfig b/configs/coreboot_defconfig
index 4db728991692..fb4d1751108f 100644
--- a/configs/coreboot_defconfig
+++ b/configs/coreboot_defconfig
@@ -56,7 +56,6 @@ CONFIG_ATAPI=y
 CONFIG_LBA48=y
 CONFIG_SYS_64BIT_LBA=y
 # CONFIG_PCI_PNP is not set
-CONFIG_SYS_NS16550_PORT_MAPPED=y
 CONFIG_SOUND=y
 CONFIG_SOUND_I8254=y
 CONFIG_CONSOLE_SCROLL_LINES=5
-- 
2.40.0.348.gf938b09366-goog