[PATCH v2] arch: arm: mach-k3: Delete tifs node in DT fixup

[Neha Malcom Francis]

Hi Andrew

On 01/05/23 20:16, Andrew Davis wrote:
> On 4/26/23 9:13 AM, Kumar, Udit wrote:
>> Hi Neha,
>>
>> On 4/26/2023 5:31 PM, Neha Malcom Francis wrote:
>>> Hi Udit
>>>
>>> On 26/04/23 16:09, Kumar, Udit wrote:
>>>> Hi Neha,
>>>>
>>>>> Hi Udit,
>>>>
>>>> [..]
>>>>
>>>>>>>
>>>>>>> I do have a general doubt; why do we have only atf-sram sub-node in
>>>>>>> msmc_sram in all other devices (j721e, j7200 and am65) except 
>>>>>>> j721s2?
>>>>>>
>>>>>> let me know, which source code you are referring to
>>>>>>
>>>>>
>>>>> In U-Boot, for j721e, j7200 and am65; they *only* contain atf-sram?
>>>>
>>>> For u-boot please see
>>>>
>>>> https://elixir.bootlin.com/u-boot/latest/source/arch/arm/dts/k3-j721s2-main.dtsi#L16
>>>>
>>>>>> I could see for j721s2 as well, in uboot[0] and Linux[1]
>>>> [..]
>>>>
>>>
>>> What I mean to ask is, why aren't there tifs or l3cache subnodes in 
>>> j721e, j7200 and am65?
>>>
>> I think,  above platform is doing in right way,
>>
>> AFAIK,  if we have to provide then we can provide size of this.
>>
>> l3-cache can not be addressable.
>>
> 
> 
> So the history here is we used to have the SRAM node in DT sized
> to the actual size in hardware. L3 cache size can be set at boot
> time (in SYSFW board-config file), and that uses up some of the
> SRAM, so the end address moves in. We could represent this as
> a reserved node inside the full SRAM node, or by shrinking the
> SRAM node and hiding this. Same story for TIFS and ATF, they
> use some variable amount of the end of SRAM.
> 
> I'd prefer being explicit and keep these nodes.
> 
> Andrew
> 

Thanks for the explanation, it does seem better to keep these nodes 
giving the complete description.

> 
>> But in any case, u-boot removes this code before passing to OS.
>>
>> https://elixir.bootlin.com/u-boot/latest/source/arch/arm/mach-k3/common.c#L354
>>
>>>>> Thanking You
>>>>> Neha Malcom Francis
>>>

-- 
Thanking You
Neha Malcom Francis