[PATCH u-boot 2/3] pci: fsl: Do not access PCI BAR0 register of PCIe Root Port

[Tom Rini]

On Thu, Apr 20, 2023 at 09:44:24PM +0200, Pali Rohár wrote:

> Freescale PCIe Root Port has PEXCSRBAR register at position of PCI BAR0.
> PCIe Root Port does not have any PCIe memory, so returns zero when trying
> to read from PCIe Root Port BAR0 and ignore any writes.
> 
> Signed-off-by: Pali Rohár <pali at kernel.org>
> Reviewed-by: Heiko Schocher <hs at denx.de>
> ---
>  drivers/pci/pcie_fsl.c | 14 ++++++++++++++
>  1 file changed, 14 insertions(+)
> 
> diff --git a/drivers/pci/pcie_fsl.c b/drivers/pci/pcie_fsl.c
> index 4600652f2b1b..06601840da85 100644
> --- a/drivers/pci/pcie_fsl.c
> +++ b/drivers/pci/pcie_fsl.c
> @@ -58,6 +58,14 @@ static int fsl_pcie_read_config(const struct udevice *bus, pci_dev_t bdf,
>  		return 0;
>  	}
>  
> +	/* Skip Freescale PCIe controller's PEXCSRBAR register */
> +	if (PCI_BUS(bdf) - dev_seq(bus) == 0 &&
> +	    PCI_DEV(bdf) == 0 && PCI_FUNC(bdf) == 0 &&
> +	    (offset & ~3) == PCI_BASE_ADDRESS_0) {
> +		*value = 0;
> +		return 0;
> +	}
> +
>  	val = PCI_CONF1_EXT_ADDRESS(PCI_BUS(bdf) - dev_seq(bus),
>  				    PCI_DEV(bdf), PCI_FUNC(bdf),
>  				    offset);

There is no "value" in this function, only "val", which in turn is local
to the function, and *valuep which we are passed by the caller, please
re-work and send v2, thanks.

-- 
Tom
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