[PATCH] arm: mach-k3: am62a7: Enable QoS for DSS

[Tom Rini]

On Fri, Apr 14, 2023 at 12:57:25PM +0530, Aradhya Bhatia wrote:

> Enable Quality of Service (QoS) blocks for Display SubSystem (DSS), by
> servicing the DSS - DDR traffic from the Real-Time (RT) queue. This is
> done by setting the DSS DMA orderID to 8.
> 
> The C7x and VPAC have been overwhelming the DSS's access to the DDR
> (when it was accessing via the Non Real-Time (NRT) Queue), primarily
> because their functional frequencies, and hence DDR accesses, were
> significantly higher than that of DSS. This led the display to flicker
> when certain edgeAI models were being run.
> 
> With the DSS traffic serviced from the RT queue, the flickering issue
> has been found to be mitigated.
> 
> The am62a qos files are auto generated from the k3 resource partitioning
> tool.
> 
> Section-3.1.12, "QoS Programming Guide", in the AM62A TRM[1], provides
> more information about the QoS, and section-14.1, "System Interconnect
> Registers", provides the register descriptions.
> 
> [1] AM62A Tech Ref Manual: https://www.ti.com/lit/pdf/spruj16
> 
> Signed-off-by: Aradhya Bhatia <a-bhatia1 at ti.com>

Applied to u-boot/master, thanks!

-- 
Tom
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