[PATCH v2 u-boot] pci: fsl: Do not access PCI BAR0 register of PCIe Root Port

Tom Rini trini at konsulko.com
Thu May 4 17:52:07 CEST 2023

On Tue, May 02, 2023 at 07:53:57PM +0200, Pali Rohár wrote:

> Freescale PCIe Root Port has PEXCSRBAR register at position of PCI BAR0.
> PCIe Root Port does not have any PCIe memory, so returns zero when trying
> to read from PCIe Root Port BAR0 and ignore any writes.
> Signed-off-by: Pali Rohár <pali at kernel.org>

Applied to u-boot/master, thanks!

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