[PATCH v3 05/17] x86: ivybridge: Ensure LPC is available for GPIO base

[Simon Glass]

The bd82x6x_get_gpio_base() does not work if the LPC is not set up.
Probe it early to avoid this problem.

In chromebook_link64 this problem shows up as an inability to read
the GPIO straps for the memory type.

Also, probing LPC can cause PCI enumeration to take place, which
significantly increases pre-relocation memory usage. LPC is sometimes
enabled directly by SPL.

Adjust the logic to probe the LPC only after relocation. This allows
chromebook_link64 to start up without a much larger
CONFIG_SYS_MALLOC_F_LEN value.

Signed-off-by: Simon Glass <sjg at chromium.org>
Reviewed-by: Bin Meng <bmeng.cn at gmail.com>
---

Changes in v3:
- Fix 'somtimes' typo
- Fix 'propblem' typo
- Squash in patch 'Set up LPC only after relocation'

Changes in v2:
- Add new patch to set up LPC only after relocation

 arch/x86/cpu/ivybridge/bd82x6x.c | 17 +++++++++--------
 drivers/sysreset/sysreset_x86.c  |  9 +++++++--
 2 files changed, 16 insertions(+), 10 deletions(-)

diff --git a/arch/x86/cpu/ivybridge/bd82x6x.c b/arch/x86/cpu/ivybridge/bd82x6x.c
index 89312a86349..417290f559e 100644
--- a/arch/x86/cpu/ivybridge/bd82x6x.c
+++ b/arch/x86/cpu/ivybridge/bd82x6x.c
@@ -31,7 +31,6 @@ DECLARE_GLOBAL_DATA_PTR;
 #define RCBA_AUDIO_CONFIG_HDA	BIT(31)
 #define RCBA_AUDIO_CONFIG_MASK	0xfe
 
-#ifndef CONFIG_HAVE_FSP
 static int pch_revision_id = -1;
 static int pch_type = -1;
 
@@ -162,15 +161,19 @@ void pch_iobp_update(struct udevice *dev, u32 address, u32 andvalue,
 
 static int bd82x6x_probe(struct udevice *dev)
 {
-	if (!(gd->flags & GD_FLG_RELOC))
-		return 0;
+	/* make sure the LPC is inited since it provides the gpio base */
+	uclass_first_device(UCLASS_LPC, &dev);
+
+	if (!IS_ENABLED(CONFIG_HAVE_FSP)) {
+		if (!(gd->flags & GD_FLG_RELOC))
+			return 0;
 
-	/* Cause the SATA device to do its init */
-	uclass_first_device(UCLASS_AHCI, &dev);
+		/* Cause the SATA device to do its init */
+		uclass_first_device(UCLASS_AHCI, &dev);
+	}
 
 	return 0;
 }
-#endif /* CONFIG_HAVE_FSP */
 
 static int bd82x6x_pch_get_spi_base(struct udevice *dev, ulong *sbasep)
 {
@@ -269,8 +272,6 @@ U_BOOT_DRIVER(bd82x6x_drv) = {
 	.name		= "bd82x6x",
 	.id		= UCLASS_PCH,
 	.of_match	= bd82x6x_ids,
-#ifndef CONFIG_HAVE_FSP
 	.probe		= bd82x6x_probe,
-#endif
 	.ops		= &bd82x6x_pch_ops,
 };
diff --git a/drivers/sysreset/sysreset_x86.c b/drivers/sysreset/sysreset_x86.c
index 8042f3994fe..4936fdb76c7 100644
--- a/drivers/sysreset/sysreset_x86.c
+++ b/drivers/sysreset/sysreset_x86.c
@@ -129,8 +129,13 @@ static int x86_sysreset_probe(struct udevice *dev)
 {
 	struct x86_sysreset_plat *plat = dev_get_plat(dev);
 
-	/* Locate the PCH if there is one. It isn't essential */
-	uclass_first_device(UCLASS_PCH, &plat->pch);
+	/*
+	 * Locate the PCH if there is one. It isn't essential. Avoid this before
+	 * relocation as we shouldn't need reset then and it needs a lot of
+	 * memory for PCI enumeration.
+	 */
+	if (gd->flags & GD_FLG_RELOC)
+		uclass_first_device(UCLASS_PCH, &plat->pch);
 
 	return 0;
 }
-- 
2.40.1.521.gf1e218fcd8-goog