[PATCH v3 01/43] x86: Allow listing MTRRs in SPL
Simon Glass
sjg at chromium.org
Fri May 5 00:57:47 CEST 2023
Move MTRR-listing code into a common file so it can be used from SPL.
Update the 'mtrr' command to call it.
Use this in SPL just before adjusting the MTRRs, so we can see the state
set up by the board. Only show it when debug is enabled.
Signed-off-by: Simon Glass <sjg at chromium.org>
---
(no changes since v1)
arch/x86/cpu/mtrr.c | 61 +++++++++++++++++++++++++++++++++++++
arch/x86/include/asm/mtrr.h | 20 ++++++++++++
arch/x86/lib/spl.c | 7 +++++
cmd/x86/mtrr.c | 60 +++---------------------------------
4 files changed, 92 insertions(+), 56 deletions(-)
diff --git a/arch/x86/cpu/mtrr.c b/arch/x86/cpu/mtrr.c
index c174dd9b3ad..40d24e6fb9b 100644
--- a/arch/x86/cpu/mtrr.c
+++ b/arch/x86/cpu/mtrr.c
@@ -30,6 +30,16 @@
DECLARE_GLOBAL_DATA_PTR;
+const char *const mtrr_type_name[MTRR_TYPE_COUNT] = {
+ "Uncacheable",
+ "Combine",
+ "2",
+ "3",
+ "Through",
+ "Protect",
+ "Back",
+};
+
/* Prepare to adjust MTRRs */
void mtrr_open(struct mtrr_state *state, bool do_caches)
{
@@ -324,3 +334,54 @@ int mtrr_set(int cpu_select, int reg, u64 base, u64 mask)
return mtrr_start_op(cpu_select, &oper);
}
+
+static void read_mtrrs_(void *arg)
+{
+ struct mtrr_info *info = arg;
+
+ mtrr_read_all(info);
+}
+
+int mtrr_list(int reg_count, int cpu_select)
+{
+ struct mtrr_info info;
+ int ret;
+ int i;
+
+ printf("Reg Valid Write-type %-16s %-16s %-16s\n", "Base ||",
+ "Mask ||", "Size ||");
+ memset(&info, '\0', sizeof(info));
+ ret = mp_run_on_cpus(cpu_select, read_mtrrs_, &info);
+ if (ret)
+ return log_msg_ret("run", ret);
+ for (i = 0; i < reg_count; i++) {
+ const char *type = "Invalid";
+ u64 base, mask, size;
+ bool valid;
+
+ base = info.mtrr[i].base;
+ mask = info.mtrr[i].mask;
+ size = ~mask & ((1ULL << CONFIG_CPU_ADDR_BITS) - 1);
+ size |= (1 << 12) - 1;
+ size += 1;
+ valid = mask & MTRR_PHYS_MASK_VALID;
+ type = mtrr_type_name[base & MTRR_BASE_TYPE_MASK];
+ printf("%d %-5s %-12s %016llx %016llx %016llx\n", i,
+ valid ? "Y" : "N", type, base & ~MTRR_BASE_TYPE_MASK,
+ mask & ~MTRR_PHYS_MASK_VALID, size);
+ }
+
+ return 0;
+}
+
+int mtrr_get_type_by_name(const char *typename)
+{
+ int i;
+
+ for (i = 0; i < MTRR_TYPE_COUNT; i++) {
+ if (*typename == *mtrr_type_name[i])
+ return i;
+ }
+
+ return -EINVAL;
+};
diff --git a/arch/x86/include/asm/mtrr.h b/arch/x86/include/asm/mtrr.h
index ca2edc7878f..2e995f54061 100644
--- a/arch/x86/include/asm/mtrr.h
+++ b/arch/x86/include/asm/mtrr.h
@@ -190,6 +190,26 @@ int mtrr_set(int cpu_select, int reg, u64 base, u64 mask);
*/
int mtrr_get_var_count(void);
+/**
+ * mtrr_list() - List the MTRRs
+ *
+ * Shows a list of all the MTRRs including their values
+ *
+ * @reg_count: Number of registers to show. You can use mtrr_get_var_count() for
+ * this
+ * @cpu_select: CPU to use. Use MP_SELECT_BSP for the boot CPU
+ * Returns: 0 if OK, -ve if the CPU was not found
+ */
+int mtrr_list(int reg_count, int cpu_select);
+
+/**
+ * mtrr_get_type_by_name() - Get the type of an MTRR given its type name
+ *
+ * @typename: Name to check
+ * Returns: MTRR type (MTRR_TYPE_...) or -EINVAL if invalid
+ */
+int mtrr_get_type_by_name(const char *typename);
+
#endif
#if ((CONFIG_XIP_ROM_SIZE & (CONFIG_XIP_ROM_SIZE - 1)) != 0)
diff --git a/arch/x86/lib/spl.c b/arch/x86/lib/spl.c
index ca1645f9d68..b9d23e6bfe1 100644
--- a/arch/x86/lib/spl.c
+++ b/arch/x86/lib/spl.c
@@ -19,6 +19,7 @@
#include <asm/cpu_common.h>
#include <asm/fsp2/fsp_api.h>
#include <asm/global_data.h>
+#include <asm/mp.h>
#include <asm/mrccache.h>
#include <asm/mtrr.h>
#include <asm/pci.h>
@@ -139,6 +140,12 @@ static int x86_spl_init(void)
arch_setup_gd(gd->new_gd);
gd->start_addr_sp = (ulong)ptr;
+ if (_LOG_DEBUG) {
+ ret = mtrr_list(mtrr_get_var_count(), MP_SELECT_BSP);
+ if (ret)
+ printf("mtrr_list failed\n");
+ }
+
/* Cache the SPI flash. Otherwise copying the code to RAM takes ages */
ret = mtrr_add_request(MTRR_TYPE_WRBACK,
(1ULL << 32) - CONFIG_XIP_ROM_SIZE,
diff --git a/cmd/x86/mtrr.c b/cmd/x86/mtrr.c
index b1691d8b65a..6ad7a123a44 100644
--- a/cmd/x86/mtrr.c
+++ b/cmd/x86/mtrr.c
@@ -10,71 +10,19 @@
#include <asm/mp.h>
#include <asm/mtrr.h>
-static const char *const mtrr_type_name[MTRR_TYPE_COUNT] = {
- "Uncacheable",
- "Combine",
- "2",
- "3",
- "Through",
- "Protect",
- "Back",
-};
-
-static void read_mtrrs(void *arg)
-{
- struct mtrr_info *info = arg;
-
- mtrr_read_all(info);
-}
-
-static int do_mtrr_list(int reg_count, int cpu_select)
-{
- struct mtrr_info info;
- int ret;
- int i;
-
- printf("Reg Valid Write-type %-16s %-16s %-16s\n", "Base ||",
- "Mask ||", "Size ||");
- memset(&info, '\0', sizeof(info));
- ret = mp_run_on_cpus(cpu_select, read_mtrrs, &info);
- if (ret)
- return log_msg_ret("run", ret);
- for (i = 0; i < reg_count; i++) {
- const char *type = "Invalid";
- uint64_t base, mask, size;
- bool valid;
-
- base = info.mtrr[i].base;
- mask = info.mtrr[i].mask;
- size = ~mask & ((1ULL << CONFIG_CPU_ADDR_BITS) - 1);
- size |= (1 << 12) - 1;
- size += 1;
- valid = mask & MTRR_PHYS_MASK_VALID;
- type = mtrr_type_name[base & MTRR_BASE_TYPE_MASK];
- printf("%d %-5s %-12s %016llx %016llx %016llx\n", i,
- valid ? "Y" : "N", type, base & ~MTRR_BASE_TYPE_MASK,
- mask & ~MTRR_PHYS_MASK_VALID, size);
- }
-
- return 0;
-}
-
static int do_mtrr_set(int cpu_select, uint reg, int argc, char *const argv[])
{
const char *typename = argv[0];
uint32_t start, size;
uint64_t base, mask;
- int i, type = -1;
+ int type = -1;
bool valid;
int ret;
if (argc < 3)
return CMD_RET_USAGE;
- for (i = 0; i < MTRR_TYPE_COUNT; i++) {
- if (*typename == *mtrr_type_name[i])
- type = i;
- }
- if (type == -1) {
+ type = mtrr_get_type_by_name(typename);
+ if (type < 0) {
printf("Invalid type name %s\n", typename);
return CMD_RET_USAGE;
}
@@ -146,7 +94,7 @@ static int do_mtrr(struct cmd_tbl *cmdtp, int flag, int argc,
if (!first)
printf("\n");
printf("CPU %d:\n", i);
- ret = do_mtrr_list(reg_count, i);
+ ret = mtrr_list(reg_count, i);
if (ret) {
printf("Failed to read CPU %s (err=%d)\n",
i < MP_SELECT_ALL ? simple_itoa(i) : "",
--
2.40.1.521.gf1e218fcd8-goog
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