[PATCH v3 6/7] ARM: dts: rockchip: rock5b: enable pcie2x1l2 and associated combphy

[Kever Yang]

On 2023/4/27 15:35, Eugen Hristev wrote:
> From: Christopher Obbard <chris.obbard at collabora.com>
>
> Enable the PCIe 2x1l 2 device and associated combphy.
> On this bus, the Rock5B has an Ethernet transceiver connected.
>
> Signed-off-by: Christopher Obbard <chris.obbard at collabora.com>
> [eugen.hristev at collabora.com: minor tweaks]
> Signed-off-by: Eugen Hristev <eugen.hristev at collabora.com>
> [jonas at kwiboo.se: add PCIe pins]
> Signed-off-by: Jonas Karlman <jonas at kwiboo.se>
Reviewed-by: Kever Yang <kever.yang at rock-chips.com>

Thanks,
- Kever
> ---
> Changes in v3:
> - s/pciE/PCIe
> Changes in v2:
>   - add pcie2x1l2_pins by Jonas
>
>   arch/arm/dts/rk3588-rock-5b-u-boot.dtsi | 22 ++++++++++++++++++++++
>   1 file changed, 22 insertions(+)
>
> diff --git a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
> index 78ffd60aaed4..d7650b7503a5 100644
> --- a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
> +++ b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
> @@ -30,13 +30,35 @@
>   	};
>   };
>   
> +&combphy0_ps {
> +	status = "okay";
> +};
> +
>   &fspim2_pins {
>   	bootph-all;
>   };
>   
> +&pcie2x1l2 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pcie2x1l2_pins &pcie_reset_h>;
> +	reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>;
> +	status = "okay";
> +};
> +
>   &pinctrl {
>   	bootph-all;
>   
> +	pcie {
> +		pcie_reset_h: pcie-reset-h {
> +			rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
> +		};
> +
> +		pcie2x1l2_pins: pcie2x1l2-pins {
> +			rockchip,pins = <3 RK_PC7 4 &pcfg_pull_none>,
> +					<3 RK_PD0 4 &pcfg_pull_none>;
> +		};
> +	};
> +
>   	usb {
>   		vcc5v0_host_en: vcc5v0-host-en {
>   			rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;