[PATCH 03/14] rockchip: rk3566-radxa-cm3-io: Update defconfig

[Kever Yang]

On 2023/4/22 09:23, Jonas Karlman wrote:
> Update defconfig for rk3566-radxa-cm3-io with new defaults. Also add
> missing supported mmc modes to sdhci node.
>
> Remove the SPL_ROCKCHIP_BACK_TO_BROM=y option, SPL is expected to load
> next stage from a FIT image and then jump to next stage not back to
> BootRom.
>
> Add CONFIG_SPL_FIT_SIGNATURE=y to let SPL verify an auto generated hash
> of FIT images. This help indicate if there is an issue loading any of
> the images to DRAM or SRAM.
>
> Extend SPL_MAX_SIZE to 0x40000, SPL is loaded to 0x0 and TF-A is loaded
> to 0x40000, use the space in between as SPL_MAX_SIZE.
>
> Add config option to include useful gpio cmd.
>
> Remove the CONFIG_NET_RANDOM_ETHADDR=y option, ethaddr and eth1addr is
> set based on cpuid read from OTP.
>
> Filter out assigned-clock props with CONFIG_OF_SPL_REMOVE_PROPS,
> U-Boot proper will read and configure assigned-clock props.
>
> Add CONFIG_SYS_NS16550_MEM32=y to use 32bit access of serial register.
>
> Signed-off-by: Jonas Karlman <jonas at kwiboo.se>
Reviewed-by: Kever Yang <kever.yang at rock-chips.com>

Thanks,
- Kever
> ---
>   arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi | 5 +++++
>   configs/radxa-cm3-io-rk3566_defconfig        | 9 +++++----
>   2 files changed, 10 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi b/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi
> index d183e935754d..a8c31fecafd8 100644
> --- a/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi
> +++ b/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi
> @@ -11,6 +11,11 @@
>   	};
>   };
>   
> +&sdhci {
> +	cap-mmc-highspeed;
> +	mmc-ddr-1_8v;
> +};
> +
>   &uart2 {
>   	clock-frequency = <24000000>;
>   	bootph-all;
> diff --git a/configs/radxa-cm3-io-rk3566_defconfig b/configs/radxa-cm3-io-rk3566_defconfig
> index 1df9cab79d51..dfaacbc8839e 100644
> --- a/configs/radxa-cm3-io-rk3566_defconfig
> +++ b/configs/radxa-cm3-io-rk3566_defconfig
> @@ -10,9 +10,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
>   CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
>   CONFIG_DEFAULT_DEVICE_TREE="rk3566-radxa-cm3-io"
>   CONFIG_ROCKCHIP_RK3568=y
> -CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
>   CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
> -CONFIG_SPL_MMC=y
>   CONFIG_SPL_SERIAL=y
>   CONFIG_SPL_STACK_R_ADDR=0x600000
>   CONFIG_TARGET_EVB_RK3568=y
> @@ -23,11 +21,12 @@ CONFIG_SYS_LOAD_ADDR=0xc00800
>   CONFIG_DEBUG_UART=y
>   CONFIG_FIT=y
>   CONFIG_FIT_VERBOSE=y
> +CONFIG_SPL_FIT_SIGNATURE=y
>   CONFIG_SPL_LOAD_FIT=y
>   CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-radxa-cm3-io.dtb"
>   # CONFIG_DISPLAY_CPUINFO is not set
>   CONFIG_DISPLAY_BOARDINFO_LATE=y
> -CONFIG_SPL_MAX_SIZE=0x20000
> +CONFIG_SPL_MAX_SIZE=0x40000
>   CONFIG_SPL_PAD_TO=0x7f8000
>   CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
>   CONFIG_SPL_BSS_START_ADDR=0x4000000
> @@ -36,6 +35,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x4000
>   # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
>   CONFIG_SPL_STACK_R=y
>   CONFIG_SPL_ATF=y
> +CONFIG_CMD_GPIO=y
>   CONFIG_CMD_GPT=y
>   CONFIG_CMD_I2C=y
>   CONFIG_CMD_MMC=y
> @@ -46,7 +46,7 @@ CONFIG_CMD_REGULATOR=y
>   # CONFIG_SPL_DOS_PARTITION is not set
>   CONFIG_SPL_OF_CONTROL=y
>   CONFIG_OF_LIVE=y
> -CONFIG_NET_RANDOM_ETHADDR=y
> +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
>   CONFIG_SPL_REGMAP=y
>   CONFIG_SPL_SYSCON=y
>   CONFIG_SPL_CLK=y
> @@ -70,6 +70,7 @@ CONFIG_PWM_ROCKCHIP=y
>   CONFIG_SPL_RAM=y
>   CONFIG_BAUDRATE=1500000
>   CONFIG_DEBUG_UART_SHIFT=2
> +CONFIG_SYS_NS16550_MEM32=y
>   CONFIG_SYSRESET=y
>   CONFIG_USB=y
>   CONFIG_USB_XHCI_HCD=y