[PATCH v5 1/6] ARM: dts: rockchip: rk3588-rock-5b-u-boot: add USB 2.0 host

[Kever Yang]

On 2023/4/19 21:40, Eugen Hristev wrote:
> Add USB 2.0 host nodes and PHYs.
>
> Co-developed-by: William Wu <william.wu at rock-chips.com>
> Signed-off-by: William Wu <william.wu at rock-chips.com>
> Signed-off-by: Eugen Hristev <eugen.hristev at collabora.com>
Reviewed-by: Kever Yang <kever.yang at rock-chips.com>

Thanks,
- Kever
> ---
> Changes in v5:
> - none
>
> Changes in v4:
> - removed u-boot,dm-spl on regulator which was useless
> - moved usb nodes to rk3588s-u-boot-dtsi
>
> Changes in v2,v3:
> - none
>
>   arch/arm/dts/rk3588-rock-5b-u-boot.dtsi | 82 +++++++++++++++++++++++
>   arch/arm/dts/rk3588s-u-boot.dtsi        | 86 +++++++++++++++++++++++++
>   2 files changed, 168 insertions(+)
>
> diff --git a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
> index bee4c32e8965..93942b105c3d 100644
> --- a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
> +++ b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
> @@ -4,6 +4,9 @@
>    */
>   
>   #include "rk3588-u-boot.dtsi"
> +#include <dt-bindings/pinctrl/rockchip.h>
> +#include <dt-bindings/input/input.h>
> +#include <dt-bindings/gpio/gpio.h>
>   
>   / {
>   	aliases {
> @@ -13,6 +16,18 @@
>   	chosen {
>   		u-boot,spl-boot-order = &sdmmc;
>   	};
> +
> +	vcc5v0_host: vcc5v0-host-regulator {
> +		compatible = "regulator-fixed";
> +		regulator-name = "vcc5v0_host";
> +		regulator-min-microvolt = <5000000>;
> +		regulator-max-microvolt = <5000000>;
> +		enable-active-high;
> +		gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>;
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&vcc5v0_host_en>;
> +		vin-supply = <&vcc5v0_sys>;
> +	};
>   };
>   
>   &sdmmc {
> @@ -20,3 +35,70 @@
>   	bootph-pre-ram;
>   	status = "okay";
>   };
> +
> +&pinctrl {
> +	usb {
> +		vcc5v0_host_en: vcc5v0-host-en {
> +			rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
> +		};
> +	};
> +};
> +
> +&usb_host0_ehci {
> +	companion = <&usb_host0_ohci>;
> +	phys = <&u2phy2_host>;
> +	phy-names = "usb2-phy";
> +	status = "okay";
> +};
> +
> +&usb_host0_ohci {
> +	phys = <&u2phy2_host>;
> +	phy-names = "usb2-phy";
> +	status = "okay";
> +};
> +
> +&usb2phy2_grf {
> +	status = "okay";
> +};
> +
> +&u2phy2 {
> +	resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>;
> +	reset-names = "phy", "apb";
> +	clock-output-names = "usb480m_phy2";
> +	status = "okay";
> +};
> +
> +&u2phy2_host {
> +	phy-supply = <&vcc5v0_host>;
> +	status = "okay";
> +};
> +
> +&usb_host1_ehci {
> +	companion = <&usb_host1_ohci>;
> +	phys = <&u2phy3_host>;
> +	phy-names = "usb2-phy";
> +	status = "okay";
> +};
> +
> +&usb_host1_ohci {
> +	phys = <&u2phy3_host>;
> +	phy-names = "usb2-phy";
> +	status = "okay";
> +};
> +
> +&usb2phy3_grf {
> +	status = "okay";
> +};
> +
> +&u2phy3 {
> +	resets = <&cru SRST_OTGPHY_U2_1>, <&cru SRST_P_USB2PHY_U2_1_GRF0>;
> +	reset-names = "phy", "apb";
> +	clock-output-names = "usb480m_phy3";
> +	status = "okay";
> +};
> +
> +&u2phy3_host {
> +	phy-supply = <&vcc5v0_host>;
> +	status = "okay";
> +};
> +
> diff --git a/arch/arm/dts/rk3588s-u-boot.dtsi b/arch/arm/dts/rk3588s-u-boot.dtsi
> index 1e225d71efc2..fb1b802fd273 100644
> --- a/arch/arm/dts/rk3588s-u-boot.dtsi
> +++ b/arch/arm/dts/rk3588s-u-boot.dtsi
> @@ -12,12 +12,98 @@
>   		status = "okay";
>   	};
>   
> +	usb_host0_ehci: usb at fc800000 {
> +		compatible = "generic-ehci";
> +		reg = <0x0 0xfc800000 0x0 0x40000>;
> +		interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH 0>;
> +		clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>;
> +		clock-names = "usbhost", "arbiter";
> +		power-domains = <&power RK3588_PD_USB>;
> +		status = "disabled";
> +	};
> +
> +	usb_host0_ohci: usb at fc840000 {
> +		compatible = "generic-ohci";
> +		reg = <0x0 0xfc840000 0x0 0x40000>;
> +		interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH 0>;
> +		clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>;
> +		clock-names = "usbhost", "arbiter";
> +		power-domains = <&power RK3588_PD_USB>;
> +		status = "disabled";
> +	};
> +
> +	usb_host1_ehci: usb at fc880000 {
> +		compatible = "generic-ehci";
> +		reg = <0x0 0xfc880000 0x0 0x40000>;
> +		interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH 0>;
> +		clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>;
> +		clock-names = "usbhost", "arbiter";
> +		power-domains = <&power RK3588_PD_USB>;
> +		status = "disabled";
> +	};
> +
> +	usb_host1_ohci: usb at fc8c0000 {
> +		compatible = "generic-ohci";
> +		reg = <0x0 0xfc8c0000 0x0 0x40000>;
> +		interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH 0>;
> +		clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>;
> +		clock-names = "usbhost", "arbiter";
> +		power-domains = <&power RK3588_PD_USB>;
> +		status = "disabled";
> +	};
> +
>   	pmu1_grf: syscon at fd58a000 {
>   		bootph-all;
>   		compatible = "rockchip,rk3588-pmu1-grf", "syscon";
>   		reg = <0x0 0xfd58a000 0x0 0x2000>;
>   	};
>   
> +	usb2phy2_grf: syscon at fd5d8000 {
> +		compatible = "rockchip,rk3588-usb2phy-grf", "syscon",
> +			     "simple-mfd";
> +		reg = <0x0 0xfd5d8000 0x0 0x4000>;
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +
> +		u2phy2: usb2-phy at 8000 {
> +			compatible = "rockchip,rk3588-usb2phy";
> +			reg = <0x8000 0x10>;
> +			interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH 0>;
> +			clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
> +			clock-names = "phyclk";
> +			#clock-cells = <0>;
> +			status = "disabled";
> +
> +			u2phy2_host: host-port {
> +				#phy-cells = <0>;
> +				status = "disabled";
> +			};
> +		};
> +	};
> +
> +	usb2phy3_grf: syscon at fd5dc000 {
> +		compatible = "rockchip,rk3588-usb2phy-grf", "syscon",
> +			     "simple-mfd";
> +		reg = <0x0 0xfd5dc000 0x0 0x4000>;
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +
> +		u2phy3: usb2-phy at c000 {
> +			compatible = "rockchip,rk3588-usb2phy";
> +			reg = <0xc000 0x10>;
> +			interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH 0>;
> +			clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
> +			clock-names = "phyclk";
> +			#clock-cells = <0>;
> +			status = "disabled";
> +
> +			u2phy3_host: host-port {
> +				#phy-cells = <0>;
> +				status = "disabled";
> +			};
> +		};
> +	};
> +
>   	sdmmc: mmc at fe2c0000 {
>   		compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc";
>   		reg = <0x0 0xfe2c0000 0x0 0x4000>;