[PATCH v5 05/10] ram: cadence: add driver for Cadence EDAC

[Marek Vasut]

On 4/24/23 03:15, Ralph Siemsen wrote:

[...]

> diff --git a/drivers/ram/cadence/ddr_ctrl.c b/drivers/ram/cadence/ddr_ctrl.c
> new file mode 100644
> index 0000000000..35544fbb95
> --- /dev/null
> +++ b/drivers/ram/cadence/ddr_ctrl.c

[...]

> +void cdns_ddr_ctrl_start(void *ddr_ctrl_basex)
> +{
> +	u32 *ddr_ctrl_base = (u32 *)ddr_ctrl_basex;
> +	u8 *base8 = (u8 *)ddr_ctrl_basex;
> +
> +	/* Start */
> +	ddrc_writeb(1, base8 + DDR_START_REG);
> +
> +	/* Wait for controller to be ready (interrupt status) */
> +	while (!(readl(base8 + DDR_INTERRUPT_STATUS) & 0x100))
> +		;

If you can, use readl_poll_timeout() or wait_for_bit*() to avoid endless 
loops .