[PATCH 05/13] x86: coreboot: Collect the address of the ACPI tables
Simon Glass
sjg at chromium.org
Mon May 8 23:23:18 CEST 2023
Hi Bin,
On Sat, 6 May 2023 at 00:05, Bin Meng <bmeng.cn at gmail.com> wrote:
>
> Hi Simon,
>
> On Fri, Mar 24, 2023 at 1:55 AM Simon Glass <sjg at chromium.org> wrote:
> >
> > Hi Bin,
> >
> > On Mon, 20 Mar 2023 at 20:44, Bin Meng <bmeng.cn at gmail.com> wrote:
> > >
> > > Hi Simon,
> > >
> > > On Tue, Feb 21, 2023 at 3:49 AM Simon Glass <sjg at chromium.org> wrote:
> > > >
> > > > Pick this up from the sysinfo tables and display it with the cbsysinfo
> > > > command. This allows the 'acpi list' command to work when booting from
> > > > coreboot.
> > > >
> > > > Signed-off-by: Simon Glass <sjg at chromium.org>
> > > > ---
> > > >
> > > > arch/x86/include/asm/cb_sysinfo.h | 2 ++
> > > > arch/x86/include/asm/coreboot_tables.h | 2 ++
> > > > arch/x86/lib/coreboot/cb_sysinfo.c | 11 +++++++++++
> > > > cmd/x86/cbsysinfo.c | 1 +
> > > > 4 files changed, 16 insertions(+)
> > > >
> > > > diff --git a/arch/x86/include/asm/cb_sysinfo.h b/arch/x86/include/asm/cb_sysinfo.h
> > > > index 0201ac6b03a..6b266149cf6 100644
> > > > --- a/arch/x86/include/asm/cb_sysinfo.h
> > > > +++ b/arch/x86/include/asm/cb_sysinfo.h
> > > > @@ -133,6 +133,7 @@
> > > > * @mtc_size: Size of MTC region
> > > > * @chromeos_vpd: Chromium OS Vital Product Data region, typically NULL, meaning
> > > > * not used
> > > > + * @rsdp: Pointer to ACPI RSDP table
> > > > */
> > > > struct sysinfo_t {
> > > > unsigned int cpu_khz;
> > > > @@ -211,6 +212,7 @@ struct sysinfo_t {
> > > > u64 mtc_start;
> > > > u32 mtc_size;
> > > > void *chromeos_vpd;
> > > > + void *rsdp;
> > > > };
> > > >
> > > > extern struct sysinfo_t lib_sysinfo;
> > > > diff --git a/arch/x86/include/asm/coreboot_tables.h b/arch/x86/include/asm/coreboot_tables.h
> > > > index f131de56a40..2d6f3db3a5f 100644
> > > > --- a/arch/x86/include/asm/coreboot_tables.h
> > > > +++ b/arch/x86/include/asm/coreboot_tables.h
> > > > @@ -422,6 +422,8 @@ struct cb_tsc_info {
> > > > #define CB_TAG_SERIALNO 0x002a
> > > > #define CB_MAX_SERIALNO_LENGTH 32
> > > >
> > > > +#define CB_TAG_ACPI_RSDP 0x0043
> > >
> > > This is using space but should be tab.
> > >
> > > > +
> > > > #define CB_TAG_CMOS_OPTION_TABLE 0x00c8
> > > >
> > > > struct cb_cmos_option_table {
> > > > diff --git a/arch/x86/lib/coreboot/cb_sysinfo.c b/arch/x86/lib/coreboot/cb_sysinfo.c
> > > > index 748fa4ee53b..a11a2587f66 100644
> > > > --- a/arch/x86/lib/coreboot/cb_sysinfo.c
> > > > +++ b/arch/x86/lib/coreboot/cb_sysinfo.c
> > > > @@ -264,6 +264,13 @@ static void cb_parse_mrc_cache(void *ptr, struct sysinfo_t *info)
> > > > info->mrc_cache = map_sysmem(cbmem->cbmem_tab, 0);
> > > > }
> > > >
> > > > +static void cb_parse_acpi_rsdp(void *ptr, struct sysinfo_t *info)
> > > > +{
> > > > + struct cb_cbmem_tab *const cbmem = (struct cb_cbmem_tab *)ptr;
> > > > +
> > > > + info->rsdp = map_sysmem(cbmem->cbmem_tab, 0);
> > > > +}
> > > > +
> > > > __weak void cb_parse_unhandled(u32 tag, unsigned char *ptr)
> > > > {
> > > > }
> > > > @@ -428,6 +435,9 @@ static int cb_parse_header(void *addr, int len, struct sysinfo_t *info)
> > > > case CB_TAG_MRC_CACHE:
> > > > cb_parse_mrc_cache(rec, info);
> > > > break;
> > > > + case CB_TAG_ACPI_RSDP:
> > > > + cb_parse_acpi_rsdp(rec, info);
> > > > + break;
> > > > default:
> > > > cb_parse_unhandled(rec->tag, ptr);
> > > > break;
> > > > @@ -454,6 +464,7 @@ int get_coreboot_info(struct sysinfo_t *info)
> > > > if (!ret)
> > > > return -ENOENT;
> > > > gd->arch.coreboot_table = addr;
> > > > + gd_set_acpi_start(map_to_sysmem(info->rsdp));
> > > > gd->flags |= GD_FLG_SKIP_LL_INIT;
> > > >
> > > > return 0;
> >
> > >
> > > Regards,
> > > Bin
> > > > diff --git a/cmd/x86/cbsysinfo.c b/cmd/x86/cbsysinfo.c
> > > > index 34fdaf5b1b1..07570b00c9a 100644
> > > > --- a/cmd/x86/cbsysinfo.c
> > > > +++ b/cmd/x86/cbsysinfo.c
> > > > @@ -363,6 +363,7 @@ static void show_table(struct sysinfo_t *info, bool verbose)
> > > > print_hex("MTC size", info->mtc_size);
> > > >
> > > > print_ptr("Chrome OS VPD", info->chromeos_vpd);
> > > > + print_ptr("RSDP", info->rsdp);
> > > > }
> > > >
> > > > static int do_cbsysinfo(struct cmd_tbl *cmdtp, int flag, int argc,
> > >
> > > I tested this patch on top of coreboot with U-Boot as a payload
> > > running on QEMU i440fx, but U-Boot does not list acpi tables.
> > >
> > > => acpi list
> > > No ACPI tables present
> >
> > Can you try 'cbsysinfo' to see what it is passing in as the RSDP?
> >
>
> 'cbsysinfo' shows RSDP is 0.
>
> => cbsysinfo
> Coreboot table at 500, decoded to 06f558a0, forwarded to 07f99000
> ...
> RSDP : 00000000
> Unimpl. : 10 37 40
> => acpi list
> No ACPI tables present
>
> coreboot boot log says:
>
> [DEBUG] Writing coreboot table at 0x07f99000
> [DEBUG] 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
> [DEBUG] 1. 0000000000001000-000000000009ffff: RAM
> [DEBUG] 2. 00000000000a0000-00000000000fffff: RESERVED
> [DEBUG] 3. 0000000000100000-0000000007f6bfff: RAM
> [DEBUG] 4. 0000000007f6c000-0000000007fa1fff: CONFIGURATION TABLES
> [DEBUG] 5. 0000000007fa2000-0000000007fcffff: RAMSTAGE
> [DEBUG] 6. 0000000007fd0000-0000000007ffffff: CONFIGURATION TABLES
> [DEBUG] 7. 00000000fec00000-00000000fec00fff: RESERVED
> [DEBUG] 8. 00000000ff800000-00000000ffffffff: RESERVED
> [DEBUG] FMAP: area COREBOOT found @ 200 (4193792 bytes)
> [DEBUG] Wrote coreboot table at: 0x07f99000, 0x2e8 bytes, checksum cb3f
> [DEBUG] coreboot table: 768 bytes.
> [DEBUG] IMD ROOT 0. 0x07fff000 0x00001000
> [DEBUG] IMD SMALL 1. 0x07ffe000 0x00001000
> [DEBUG] CONSOLE 2. 0x07fde000 0x00020000
> [DEBUG] TIME STAMP 3. 0x07fdd000 0x00000910
> [DEBUG] AFTER CAR 4. 0x07fd0000 0x0000d000
> [DEBUG] RAMSTAGE 5. 0x07fa1000 0x0002f000
> [DEBUG] COREBOOT 6. 0x07f99000 0x00008000
> [DEBUG] IRQ TABLE 7. 0x07f98000 0x00001000
> [DEBUG] ACPI 8. 0x07f74000 0x00024000
> [DEBUG] SMBIOS 9. 0x07f6c000 0x00008000
Can you check why coreboot is not passing it through? It should
provide the RSDP in LB_TAG_ACPI_RSDP
Regards,
Simon
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