[PATCH 1/1] config: CONFIG_SPL_SIZE_LIMIT for VisionFive 2

Bo Gan ganboing at gmail.com
Wed May 17 02:17:20 CEST 2023

@Heinrich Some background information I discovered by experimenting with my vf2 board:

The only reasonable place to load SPL is the L2 LIM, which is 2M in size mapped at
0x8000000. This region consists of 16 0x20000 sized regions, each one can be used as
either L2 cache way or SRAM (not both). From top to bottom, you have way 0-15. When
ways are enabled, they can't be disabled without reset. Effectively, as you enabling
more and more L2 cache, this SRAM region shrinks. The way 0 is always enabled, so SPL
can only use at most 0x1e0000 bytes of memory.

On 5/16/23 12:56 PM, Heinrich Schuchardt wrote:
> https://github.com/starfive-tech/Tools/commit/8c5acc4e5eb7e4ad012463b05a5e3dbbfed1c38d
> seems to have changed the limit in the tooling.

I don't know how they derive the number 180048, but my guess is they just pick some
number that fits their u-boot build. For correctness, it really depends on how ROM is
loading SPL, and where does ROM allocate its data/stack during loading, so it won't
collide with the SPL being loaded. It might also be that ROM uses S7 DTIM to load SPL,
and doesn't touch L2 LIM at all. The ROM is close-sourced, thus, not very easy to know
without reverse-engineering it. The defconfig already defines

> https://github.com/u-boot/u-boot/blob/6e1852c/configs/starfive_visionfive2_defconfig#L37

256KiB of SPL sounds like a reasonable number to me. 128KiB might be a little bit small
when you have max loglevels enabled, and -DDEBUG. I think we can probably just change

More information about the U-Boot mailing list