[PATCH v4 1/7] dt-bindings: clock: Add StarFive JH7110 PLL clock generator

[Conor Dooley]

On Tue, May 23, 2023 at 01:10:06PM +0200, Torsten Duwe wrote:
> On Tue, 23 May 2023 09:28:39 +0100
> Conor Dooley <conor.dooley at microchip.com> wrote:
> 
> > On Tue, May 23, 2023 at 10:56:43AM +0800, Xingyu Wu wrote:
> > > On 2023/5/19 22:16, Conor Dooley wrote:
> > > > On Fri, May 19, 2023 at 03:57:33PM +0200, Torsten Duwe wrote:
> > > >> On Fri, May 12, 2023 at 10:20:30AM +0800, Xingyu Wu wrote:
> > > >> [...]
> 
> > > >> > +/* PLL clocks */
> > > >> > +#define JH7110_CLK_PLL0_OUT			0
> > > >> > +#define JH7110_CLK_PLL1_OUT			1
> > > >> > +#define JH7110_CLK_PLL2_OUT			2
> > > >> 
> > > >> In U-Boot commit 58c9c60b Yanhong Wang added:
> > > >> 
> > > >> +
> > > >> +#define JH7110_SYSCLK_PLL0_OUT                       190
> > > >> +#define JH7110_SYSCLK_PLL1_OUT                       191
> > > >> +#define JH7110_SYSCLK_PLL2_OUT                       192
> > > >> +
> > > >> +#define JH7110_SYSCLK_END                    193
> [...]
> > > > Ohh, that's not good.. If you pass the U-Boot dtb to Linux it
> > > > won't understand the numbering. The headers are part of the
> > > > dt-binding :/
> 
> In fact, the clock index >= 190 makes linux hang on boot, waiting with
> EPROBE_DEFER for every device's clock, because the sysclk driver errors
> out with EINVAL (jh7110_sysclk_get()).

Yup, that's about what I expected to happen.

> > > Because PLL driver is separated from SYSCRG drivers in Linux, the
> > > numbering starts from 0. But in Uboot, the PLL driver is included
> > > in the SYSCRG driver, and the number follows the SYSCRG.
> > 
> > Unfortunately, how you choose to construct your drivers has nothing to
> > do with this.
> > These defines/numbers appear in the dts and are part of the DT ABI.
> > The same dts is supposed to work for Linux & U-Boot.
> 
> The JH7110 has 6 blocks of 64k iomem in that functional area:
> {SYS,STG,AON} x {CRG,SYSCON}. None of these has 190 clocks.
> The good news: the current DTS, as proposed here and in U-Boot master,
> provides nodes for all 6 entities. The bad news is that the clock
> assignments to those nodes and their numbering is messed up.
> 
> AFAICT PLL{0,1,2} _are_ generated in SYS_SYSCON and thus U-Boot gets it
> wrong, in addition to the erroneous DTS.

The numbers are kinda hocus-pocus anyway, they are just made up since the
clock numbering usually isn't something with a nice TRM to go and
reference (unlike interrupts which usually are documented in that way).
It is very helpful to make them aligned some register/bit positions or,
but that is not required.
IOW U-Boot is not wrong per se to use 190 instead of 0, but it is wrong
to have different numbers in both places.

It sounds like you're saying that (and I have not looked) the U-Boot dts
actually has structural difference w.r.t. what provides which clock?
If so, that'll need to be fixed independently of the numbering problem.

Otherwise Xingyu & Yanhong should coordinate on which is the "correct"
way of doing things & do it in both places.

Thanks,
Conor.
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