[PATCH v2] PCI: zynqmp: Add ZynqMP NWL PCIe root port driver

[Stefan Roese]

Hi Michal,

On 5/25/23 17:53, Michal Simek wrote:
> 
> 
> On 5/25/23 11:49, Stefan Roese wrote:
>> This patch adds the PCIe controller driver for the Xilinx / AMD ZynqMP
>> NWL PCIe Bridge as root port. The driver source is partly copied from
>> the Linux PCI driver and modified to enable usage in U-Boot (e.g.
>> simplified and interrupt support removed).
>>
>> Signed-off-by: Stefan Roese <sr at denx.de>
>> Cc: Simon Glass <sjg at chromium.org>
>> Cc: Pali Rohár <pali at kernel.org>
>> Cc: Bin Meng <bmeng.cn at gmail.com>
>> Cc: Michal Simek <michal.simek at amd.com>
>> ---
>> v2:
>> - Remove some unused members from struct nwl_pcie
>> - Fix usage of dev_seq() in nwl_pcie_config_address()
>> - Remove writing to PCI_PRIMARY_BUS reg as this is done by the
>>    common U-Boot PCI code later
>>
>>   MAINTAINERS                   |   1 +
>>   drivers/pci/Kconfig           |   7 +
>>   drivers/pci/Makefile          |   1 +
>>   drivers/pci/pcie-xilinx-nwl.c | 352 ++++++++++++++++++++++++++++++++++
>>   4 files changed, 361 insertions(+)
>>   create mode 100644 drivers/pci/pcie-xilinx-nwl.c
> 
> Tested-by: Michal Simek <michal.simek at amd.com>
> Acked-by: Michal Simek <michal.simek at amd.com>

Thanks for testing.

> I am happy to take this via my tree if you like.

Please do so.

> We should also enable this driver by default in 
> xilinx_zynqmp_virt_defconfig and likely any pcie driver to be able to 
> test it.

Perfect. Please do this.

> I used e1000 based card and it works as expected.

Good.

Thanks,
Stefan