[PATCH v1] common/memsize.c: Fix get_ram_size() when cache is enabled

[Francesco Dolcini]

On Fri, May 26, 2023 at 12:15:10PM -0400, Tom Rini wrote:
> On Thu, May 25, 2023 at 03:01:13PM +0200, Francesco Dolcini wrote:
> 
> > From: Emanuele Ghidoli <emanuele.ghidoli at toradex.com>
> > 
> > Ensure that every write is flushed to memory and afterward reads are
> > from memory.
> > Since the algorithm rely on the fact that accessing to not existent
> > memory lead to write at addr / 2 without this modification accesses
> > to aliased (not physically present) addresses are cached and
> > wrong size is returned.
> > 
> > This was discovered while working on a TI AM625 based board
> > where cache is normally enabled, see commit c02712a74849 ("arm: mach-k3: Enable dcache in SPL").
> > 
> > Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli at toradex.com>
> > Signed-off-by: Francesco Dolcini <francesco.dolcini at toradex.com>
> > ---
> >  common/memsize.c | 14 ++++++++++++++
> >  1 file changed, 14 insertions(+)
> 
> Ah, interesting.  Have you put this through a full CI loop via Azure
> for example, since this is common code?  That's my real concern here,
> thanks.

v2 is coming, your were right on having concerns.

Francesco