[PATCH 3/3] arm: dts: imx8mp: Sync with Linux 6.3

[Tim Harvey]

On Tue, May 30, 2023 at 10:28 AM Adam Ford <aford173 at gmail.com> wrote:
>
> On Tue, May 30, 2023 at 12:23 PM Tim Harvey <tharvey at gateworks.com> wrote:
> >
> > On Mon, May 29, 2023 at 10:45 AM Adam Ford <aford173 at gmail.com> wrote:
> > >
> > > On Wed, May 24, 2023 at 9:02 PM Fabio Estevam <festevam at gmail.com> wrote:
> > > >
> > > > Hi Tim,
> > > >
> > > > On Fri, May 19, 2023 at 8:00 PM Tim Harvey <tharvey at gateworks.com> wrote:
> > > >
> > > > > Fabio,
> > >
> > > + Marek
> > > I am adding Marek since he did the HSIO power domain driver.
> > >
> > > > >
> > > > > There's more to be done here also. With this patch, and with the
> > > > > spba-bus added to u-boot.dtsi, if you try to enable usb (usb start)
> > > > > you get:
> > > > > starting USB...
> > > > > Bus usb at 38200000:
> > > > > Enable clock-controller at 30380000 failed
> > > > > probe failed, error -2
> > > > > No working controllers found
> > > >
> > > > Does this help?
> > >
> > > A bit.  I finally got some time to try to troubleshoot USB on my 8MP.
> > >
> > > >
> > > > --- a/drivers/clk/imx/clk-imx8mp.c
> > > > +++ b/drivers/clk/imx/clk-imx8mp.c
> > > > @@ -337,8 +337,8 @@ static int imx8mp_clk_probe(struct udevice *dev)
> > > >         clk_dm(IMX8MP_CLK_UART2_ROOT, imx_clk_gate4("uart2_root_clk",
> > > > "uart2", base + 0x44a0, 0));
> > > >         clk_dm(IMX8MP_CLK_UART3_ROOT, imx_clk_gate4("uart3_root_clk",
> > > > "uart3", base + 0x44b0, 0));
> > > >         clk_dm(IMX8MP_CLK_UART4_ROOT, imx_clk_gate4("uart4_root_clk",
> > > > "uart4", base + 0x44c0, 0));
> > > > -       clk_dm(IMX8MP_CLK_USB_ROOT, imx_clk_gate4("usb_root_clk",
> > > > "usb_core_ref", base + 0x44d0, 0));
> > > > -       clk_dm(IMX8MP_CLK_USB_PHY_ROOT,
> > >
> > > IMX8MP_CLK_USB_PHY_ROOT is also referenced in the device tree, so I
> > > don't think we can delete it. I had  keep IMX8MP_CLK_USB_ROOT, and
> > > IMX8MP_CLK_USB_PHY_ROOT while also adding IMX8MP_CLK_USB_SUSP.
> > >
> > > > imx_clk_gate4("usb_phy_root_clk", "usb_phy_ref", base + 0x44f0, 0));
> > > > +       clk_dm(IMX8MP_CLK_USB_ROOT, imx_clk_gate4("usb_root_clk",
> > > > "hsio_axi", base + 0x44d0, 0));
> > > > +       clk_dm(IMX8MP_CLK_USB_SUSP, imx_clk_gate4("usb_suspend_clk",
> > > > "osc_32k", base + 0x44d0, 0));
> > > >         clk_dm(IMX8MP_CLK_USDHC1_ROOT,
> > > > imx_clk_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0));
> > > >         clk_dm(IMX8MP_CLK_USDHC2_ROOT,
> > > > imx_clk_gate4("usdhc2_root_clk", "usdhc2", base + 0x4520, 0));
> > > >         clk_dm(IMX8MP_CLK_WDOG1_ROOT, imx_clk_gate4("wdog1_root_clk",
> > > > "wdog", base + 0x4530, 0));
> > >
> > > At this point, the missing clock errors go away, but it hangs.  I
> > > updated my 8MP USB clocks based on the latest Linux kernel so my
> > > clocks looks like:
> > >
> > > clk_dm(IMX8MP_CLK_USB_ROOT, imx_clk_gate2("usb_root_clk", "hsio_axi",
> > > base + 0x44d0, 0));
> > > clk_dm(IMX8MP_CLK_USB_SUSP, imx_clk_gate2("usb_suspend_clk",
> > > "clock-osc-24m", base + 0x44d0, 0));
> > > clk_dm(IMX8MP_CLK_USB_PHY_ROOT, imx_clk_gate4("usb_phy_root_clk",
> > > "usb_phy_ref", base + 0x44f0, 0));
> > >
> > > The linux kernel uses gate2 for USB_ROOT and USB_SUSP while gate4 is
> > > used for IMX8MP_CLK_USB_PHY_ROOT.  I didn't verify this against the
> > > reference manual.
> > >
> > > With some debugging enabled, it looks to me like it might be
> > > power-domain related, but I am not 100% certain.
> > > When I start the USB, it appears to go through some clocks, and start
> > > one power domain, but I think we have a power-domain chain where one
> > > power domain starts another.  I saw a patch on another thread for
> > > enabling parent power-domains, but it didn't seem to help me.
> > >
> > > u-boot=> usb start
> > > starting USB...
> > > Bus usb at 38200000: ofnode_read_prop: maximum-speed: <not found>
> > > ofnode_read_prop: dr_mode: host
> > > dev_power_domain_on usb at 32f10108
> > > ofnode_read_prop: assigned-clock-rates: <not found>
> > > Looking for clock-controller at 30380000
> > > Looking for clock-controller at 30380000
> > >    - result for clock-controller at 30380000: clock-controller at 30380000 (ret=0)
> > >    - result for clock-controller at 30380000: clock-controller at 30380000 (ret=0)
> > > Looking for clock-controller at 30380000
> > > Looking for clock-controller at 30380000
> > >    - result for clock-controller at 30380000: clock-controller at 30380000 (ret=0)
> > >    - result for clock-controller at 30380000: clock-controller at 30380000 (ret=0)
> > > ofnode_read_prop: dr_mode: host
> > >
> > > <hang>
> > >
> > > I added some debug code to the imx8mp_hsiomix_on in HSIOmix power
> > > domain driver, and it doesn't appear to be getting called, yet
> > > dev_power_domain_on usb at 32f10108 should be invoking it.
> > >
> > > I am not positive it's a power domain issue, that's my first guess.
> > >
> > >
> > > Tim - have you had any success?
> > >
> >
> > Adam,
> >
> > No success here yet but I don't have any time to work on it for at
> > least another week.
>
> No worries. I'll try to spend some more time this week, and keep you
> informed of any progress.  I'd like to see the USB working too.
>

Adam,

Thanks for keeping me in the loop. For my boards I also need to add
vbus regulator enable to the dwc controller (which I've worked on a
bit but have not submitted anything yet) and eventually gpio dual-role
based detect/configure as well (which I have not worked on and
currently just force dr-mode to host in a u-boot.dtsi file to deal
with).

Best Regards,

Tim