[PATCH V3 0/3] doc: falcon: riscv: Falcon Mode boot on RISC-V

[Randolph]

Changes in v3:
- Change by suggestions in falcon.rst 
- Move the board-related code to arch-specific code,
  its the issue when enabling LOAD_FIT_OPENSBI_OS_BOOT
- Add SPL_PAYLOAD_ARGS_ADDR to defconfig.
  This is the address that SPL copies into defconfig.

Randolph (3):
  doc: falcon: riscv: Falcon Mode boot on RISC-V
  spl: riscv: falcon: move fdt blob to specified address
  configs: andes: add the fdt blob address for SPL copy to

 board/AndesTech/ae350/ae350.c           |  25 ----
 common/spl/Kconfig                      |   2 +-
 common/spl/spl_opensbi.c                |  16 +++
 configs/ae350_rv32_falcon_defconfig     |   1 +
 configs/ae350_rv32_falcon_xip_defconfig |   1 +
 configs/ae350_rv64_falcon_defconfig     |   1 +
 configs/ae350_rv64_falcon_xip_defconfig |   1 +
 doc/develop/falcon.rst                  | 171 ++++++++++++++++++++++++
 8 files changed, 192 insertions(+), 26 deletions(-)

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2.34.1