[PATCH 1/5] clk: renesas: Confirm all clock & reset changes on RZ/G2L

[Marek Vasut]

On 11/15/23 18:40, Paul Barker wrote:
> When enabling/disabling a clock or reset signal, confirm that the change
> has completed before returning from the function. A somewhat arbitrary
> 100ms timeout is defined to ensure that the system doesn't lock up in
> the case of an error.
> 
> Since we need to dynamically determine if we're waiting for a 0 bit or a
> 1 bit, it's easier to use wait_for_bit_32() than readl_poll_timeout().
> 
> This change is needed for reliable initialization of the I2C driver
> which is added in a following patch.
> 
> Fixes: 1918ff5c95be ("clk: renesas: Add RZ/G2L & RZ/G2LC CPG driver")
> Signed-off-by: Paul Barker <paul.barker.ct at bp.renesas.com>

Reviewed-by: Marek Vasut <marek.vasut+renesas at mailbox.org>