TPM SPI issue

[Sean Anderson]

Hi Niek,

On 11/29/23 18:58, niek.nooijens at omron.com wrote:
> Hi Fabio
> 
> I'm using the socfpga_cyclone5 with the designwire_spi driver.
> I added the TPM to the devicetree as so:
> &spi0 {
>       status = "okay";
>       num-cs = <2>;
>       mram0 at 0 {
>             compatible = "spi-dev";
>             reg = <0>;
>             spi-max-frequency = <1000000>;
>       };
>       tpm at 1 { // slm9670 - U144
>             compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
>             reg = <1>;
>             spi-max-frequency = <1000000>;
>       };
> };

The DW SPI device does not support holding the CS low between separate reads/writes.
The easiest fix is to use a GPIO CS. However, you can also rewrite the SPI slave
driver to use mem_ops, which will ensure that the CS stays high for a transaction.
However, this may not be possible for all slaves. For more info, have a look at
commit fec7bf0460d ("spi: dw: Add mem_ops").

--Sean

> NIek
> ________________________________
> 差出人: Fabio Estevam <festevam at gmail.com>
> 送信日時: 2023年11月29日 22:17
> 宛先: Niek Nooijens / OC-IAB PBD-C DEVEL 1-1 <niek.nooijens at omron.com>
> CC: u-boot at lists.denx.de <u-boot at lists.denx.de>
> 件名: Re: TPM SPI issue
> 
> [festevam at gmail.com からのメールを受け取る頻度は高くありません。これが問題である可能性の理由については、https://aka.ms/LearnAboutSenderIdentification をご覧ください。]
> 
> Hi Niek,
> 
> On Wed, Nov 29, 2023 at 9:51 AM niek.nooijens at omron.com
> <niek.nooijens at omron.com> wrote:
>>
>> Hi there
>>
>> I have the same issue as here:
>> https://jpn01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fcommunity.infineon.com%2Ft5%2FOPTIGA-TPM%2FI-MX8-TPM-SLB9670-SPI-Com-Error%2Ftd-p%2F472533&data=05%7C01%7Cniek.nooijens%40omron.com%7C0ed9342c6f4e4d14dbbe08dbf0dd80b5%7C0ecff5a94bef4a7b96eca96579b4ac37%7C0%7C0%7C638368606354451409%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&sdata=D3f09RUX4i0EcgQiUC4rv3y1VP3A5Ka3ozAR8dXden8%3D&reserved=0<https://community.infineon.com/t5/OPTIGA-TPM/I-MX8-TPM-SLB9670-SPI-Com-Error/td-p/472533>
>>
>> apparently the CS is released in between responses. Can you help me solve this?
> 
> Which SoC are you using?
> 
> In case you are using drivers/spi/mxc_spi.c, there was a commit in the
> kernel driver that
> allowed to put the CS line in low when idle:
> 
> https://jpn01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgit.kernel.org%2Fpub%2Fscm%2Flinux%2Fkernel%2Fgit%2Fstable%2Flinux.git%2Fcommit%2F%3Fh%3Dv6.6.3%26id%3D6a983ff5102ff0d859df05ca3f5cf2f6a17c0fad&data=05%7C01%7Cniek.nooijens%40omron.com%7C0ed9342c6f4e4d14dbbe08dbf0dd80b5%7C0ecff5a94bef4a7b96eca96579b4ac37%7C0%7C0%7C638368606354458890%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&sdata=Q3feQjDcyArxhwoehGB3D%2Fwnq0phPPs3pb8jdmkdaSg%3D&reserved=0<https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v6.6.3&id=6a983ff5102ff0d859df05ca3f5cf2f6a17c0fad>