[PATCH 07/16] clk: renesas: Add RZ/G2L CPG driver

[Marek Vasut]

On 10/4/23 10:15, Paul Barker wrote:

[...]

>>>    config R9A07G044L
>>>    	bool "Renesas R9A07G044L SoC"
>>> +	imply CLK_R9A07G044
>>
>> Why not CLK_R9A07G044L (with L at the end) ?
> 
> The driver will also support the RZ/G2LC (R9A07G044C) when support for
> that SoC is added in a later patch series.

Ah, please, do add this explanation into the commit message.

This is really valuable piece of information to de-confuse whoever is 
looking at this naming scheme, really.

>>> +/* Mux clock tables */
>>> +static const char * const sel_pll3_3[] = { ".pll3_533", ".pll3_400" };
>>> +static const char * const sel_pll5_4[] = { ".pll5_foutpostdiv", ".pll5_fout1ph0" };
>>> +static const char * const sel_pll6_2[]	= { ".pll6_250", ".pll5_250" };
>>
>> Is this mixed tabs and spaces here ?
>>
>> (please fix this in Linux too)
> 
> I've tried to minimize changes between the u-boot and Linux drivers, so
> this mixed tabs/spaces issue, parenthesis around numbers in defines,
> etc, is an exact copy of what was accepted into the mainline kernel. The
> hope is that we can more easily port fixes from Linux to u-boot if the
> code remains as similar as possible.

Send patch to Geert on Linux side too and problem should be solved.