[PATCH v4 2/2] arm: dts: j7200: dts sync with Linux 6.6-rc1

[reidt]

On 12:04-20231005, Nishanth Menon wrote:
> On 09:04-20231005, reidt wrote:
> [...]
> > > > -	clk_200mhz: dummy_clock_200mhz {
> > > > -		compatible = "fixed-clock";
> > > > -		#clock-cells = <0>;
> > > > -		clock-frequency = <200000000>;
> > > > -		bootph-pre-ram;
> > > > +		bootph-all;
> > > 
> > > Here and else where in the r5 file: why switch from pre-ram to bootph-all
> > > ? dont we need these prior to ddr initialization?
> > >
> > 
> > Due to the change in how booth-pre-ram works [0], bootph-pre-ram alone no
> > longer works. U-boot docs Pre-Relocation Support section says some-ram
> > can be used for u-boot prior to reloc, but not spl. So like Massimo
> > mentioned in the linked discussion, some-ram + pre-ram can work, as well
> > as -all. Outside of affecting the TPL phase, I'm not sure I know of a
> > difference in regards to how it affects pre-ddr.
> > 
> > 
> > [0]: https://lore.kernel.org/u-boot/CAPnjgZ3MgWX8T0A0SofphEr_Xd77pE3hte9DNye1RuBVeB9N8Q@mail.gmail.com/
> > 
> 
> Also see:
> https://github.com/u-boot/u-boot/commit/0cb6515cdab483ce8b30680803cbed0a63044cdc
> https://github.com/u-boot/u-boot/commit/7e5b6f1cff846218b824a4d906e2831c15864a53
> https://lore.kernel.org/all/3376a0eb-57f4-416a-b4b8-86cee769d6eb@siemens.com/
> etc..
> 
> as a rule of thumb: u-boot.dtsi uses bootph-all; r5-xyz.dts uses booth-pre-ram
> 
> Where this failed completely is when A53 started using booth-pre-ram in
> which case the u-boot stages failed on A53 side.
> 
> The rule of thumb I explained works across silicon (bar other issues).

Ah, good to know! Appreciate the info, I'll have v5 up soon with that
change.

Thanks,
Reid
 
> -- 
> Regards,
> Nishanth Menon
> Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3  1A34 DDB5 849D 1736 249D