[PATCH v2 3/5] clk: rockchip: rk3588: support aclk_top_root set 750M

[Kever Yang]

On 2023/10/11 18:29, Elaine Zhang wrote:
> aclk_top_root choose a parent clock that does not change.
>
> Signed-off-by: Elaine Zhang <zhangqing at rock-chips.com>
Reviewed-by: Kever Yang <kever.yang at rock-chips.com>

Thanks,
- Kever
> ---
>   drivers/clk/rockchip/clk_rk3588.c | 10 ++++++++--
>   1 file changed, 8 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/clk/rockchip/clk_rk3588.c b/drivers/clk/rockchip/clk_rk3588.c
> index c86176264147..7ba037ad72ba 100644
> --- a/drivers/clk/rockchip/clk_rk3588.c
> +++ b/drivers/clk/rockchip/clk_rk3588.c
> @@ -306,12 +306,18 @@ static ulong rk3588_top_set_clk(struct rk3588_clk_priv *priv,
>   
>   	switch (clk_id) {
>   	case ACLK_TOP_ROOT:
> -		src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate);
> +		if (!(priv->cpll_hz % rate)) {
> +			src_clk = ACLK_TOP_ROOT_SRC_SEL_CPLL;
> +			src_clk_div = DIV_ROUND_UP(priv->cpll_hz, rate);
> +		} else {
> +			src_clk = ACLK_TOP_ROOT_SRC_SEL_GPLL;
> +			src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate);
> +		}
>   		assert(src_clk_div - 1 <= 31);
>   		rk_clrsetreg(&cru->clksel_con[8],
>   			     ACLK_TOP_ROOT_DIV_MASK |
>   			     ACLK_TOP_ROOT_SRC_SEL_MASK,
> -			     (ACLK_TOP_ROOT_SRC_SEL_GPLL <<
> +			     (src_clk <<
>   			      ACLK_TOP_ROOT_SRC_SEL_SHIFT) |
>   			     (src_clk_div - 1) << ACLK_TOP_ROOT_DIV_SHIFT);
>   		break;