[PULL] u-boot-riscv/master

[Leo Liang]

Hi Tom,

The following changes since commit 9a0cf3993f71043ba08c315572c54622de42d447:

  Merge branch '2023-10-17-spl-test-some-load-methods' (2023-10-18 08:28:00 -0400)

are available in the Git repository at:

  https://source.denx.de/u-boot/custodians/u-boot-riscv.git 

for you to fetch changes up to bc5a50452bd42029d6587e1596b44ff235655e90:

  riscv: Add Zbb support for building U-Boot (2023-10-19 17:29:50 +0800)

CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/18215
----------------------------------------------------------------

+ riscv: Add Zbb support
+ riscv: Add preliminary RISC-V falcon mode support
+ riscv: Remove dram_init_banksize()
+ andes: rearrange PLICSW scheme
+ visionfive2: enable bootstage configs

----------------------------------------------------------------
Chanho Park (1):
      configs: visionfive2: enable bootstage configs

Heinrich Schuchardt (1):
      riscv: remove dram_init_banksize()

Mayuresh Chitale (1):
      riscv: binman: Fix compilation error

Randolph (8):
      riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy
      spl: riscv: opensbi: change the default os_type as varible
      riscv: kconfig: introduce SPL_LOAD_FIT_OPENSBI_OS_BOOT symbol
      riscv: dts: binman: add condition for opensbi os boot
      Makefile: delete file *.itb when make clean
      spl: riscv: add os type for next booting stage
      andes: config: add riscv falcon mode for ae350 platform
      riscv: spl: andes: Move the DTB in front of kernel

Yu Chien Peter Lin (1):
      riscv: Add Zbb support for building U-Boot

 Makefile                                |   2 +-
 arch/riscv/Kconfig                      |  99 +++++++++++++++++++++++++++++++
 arch/riscv/Makefile                     |   5 +-
 arch/riscv/cpu/generic/dram.c           |  16 -----
 arch/riscv/dts/binman.dtsi              |  38 ++++++++++--
 arch/riscv/include/asm/string.h         |  18 ++++++
 arch/riscv/lib/Makefile                 |   3 +
 arch/riscv/lib/andes_plicsw.c           |  24 ++++----
 arch/riscv/lib/strcmp_zbb.S             |  81 +++++++++++++++++++++++++
 arch/riscv/lib/strlen_zbb.S             | 101 ++++++++++++++++++++++++++++++++
 arch/riscv/lib/strncmp_zbb.S            |  94 +++++++++++++++++++++++++++++
 board/AndesTech/ae350/ae350.c           |  25 ++++++++
 common/spl/spl_fit.c                    |   3 +-
 common/spl/spl_opensbi.c                |  31 ++++++----
 configs/ae350_rv32_falcon_defconfig     |  60 +++++++++++++++++++
 configs/ae350_rv32_falcon_xip_defconfig |  61 +++++++++++++++++++
 configs/ae350_rv64_falcon_defconfig     |  60 +++++++++++++++++++
 configs/ae350_rv64_falcon_xip_defconfig |  61 +++++++++++++++++++
 configs/starfive_visionfive2_defconfig  |   2 +
 19 files changed, 738 insertions(+), 46 deletions(-)
 create mode 100644 arch/riscv/lib/strcmp_zbb.S
 create mode 100644 arch/riscv/lib/strlen_zbb.S
 create mode 100644 arch/riscv/lib/strncmp_zbb.S
 create mode 100644 configs/ae350_rv32_falcon_defconfig
 create mode 100644 configs/ae350_rv32_falcon_xip_defconfig
 create mode 100644 configs/ae350_rv64_falcon_defconfig
 create mode 100644 configs/ae350_rv64_falcon_xip_defconfig

 Best regards,
 Leo