[PATCH 2/4] arm: dts: Add support for AM62x LP SK

[Nitin Yadav]

Hi Nishanth,

On 27/09/23 17:22, Nishanth Menon wrote:
> On 13:51-20230927, Nitin Yadav wrote:
>> The AM62x LP SK board is similar to the AM62x SK board,
>> but has some significant changes that requires different
>> device tree.
>>
>> The differences are mainly:
>> - AM62x SoC in the AMC package that meets AECQ100 automotive standard.
>> - LPDDR4 versus DDR4 on the AM62x SK.
>> - TPS65219 PMIC instead of discrete regulators.
>> - IO expander pin names are wired differently.
>> - Second ethernet port is currently disabled as the boards do not have
>>   the part physically installed.
>> - OSPI NAND vs OSPI NOR.
>> - No WLAN chip instead a SDIO M.2 connector.
>>
>> Signed-off-by: Nitin Yadav <n-yadav at ti.com>
>> ---
>>  arch/arm/dts/Makefile                         |    2 +
>>  arch/arm/dts/k3-am62-lp-sk-u-boot.dtsi        |    9 +
>>  arch/arm/dts/k3-am62-lp-sk.dts                |  231 ++
> 
>>  arch/arm/dts/k3-am62-r5-lp-sk.dts             |   21 +
>>  arch/arm/dts/k3-am62x-ddr-lp4-50-800-800.dtsi | 2190 +++++++++++++++++
>>  5 files changed, 2453 insertions(+)
>>  create mode 100644 arch/arm/dts/k3-am62-lp-sk-u-boot.dtsi
>>  create mode 100644 arch/arm/dts/k3-am62-lp-sk.dts
>>  create mode 100644 arch/arm/dts/k3-am62-r5-lp-sk.dts
>>  create mode 100644 arch/arm/dts/k3-am62x-ddr-lp4-50-800-800.dtsi
>>
>> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
>> index bde2176ec7..72ea57885f 100644
>> --- a/arch/arm/dts/Makefile
>> +++ b/arch/arm/dts/Makefile
>> @@ -1337,6 +1337,8 @@ dtb-$(CONFIG_SOC_K3_AM642) += k3-am642-evm.dtb \
>>  
>>  dtb-$(CONFIG_SOC_K3_AM625) += k3-am625-sk.dtb \
>>  			      k3-am625-r5-sk.dtb \
>> +			      k3-am62-lp-sk.dtb \
>> +			      k3-am62-r5-lp-sk.dtb \
>>  			      k3-am625-beagleplay.dtb \
>>  			      k3-am625-r5-beagleplay.dtb \
>>  			      k3-am625-verdin-wifi-dev.dtb \
>> diff --git a/arch/arm/dts/k3-am62-lp-sk-u-boot.dtsi b/arch/arm/dts/k3-am62-lp-sk-u-boot.dtsi
>> new file mode 100644
>> index 0000000000..7da94fe4b6
>> --- /dev/null
>> +++ b/arch/arm/dts/k3-am62-lp-sk-u-boot.dtsi
>> @@ -0,0 +1,9 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * AM62x LP SK dts file for SPLs
>> + * Copyright (C) 2021-2023 Texas Instruments Incorporated - https://www.ti.com/
>> + */
>> +
>> +#include "k3-am62x-sk-common-u-boot.dtsi"
>> +
>> +#include "k3-am62-lp-sk-binman.dtsi"
> 
> Are you sure you don't need the dt phase properties for regulators for
> mmc to work?
you have added bootph-* flags to those nodes too .?

> 
>> diff --git a/arch/arm/dts/k3-am62-lp-sk.dts b/arch/arm/dts/k3-am62-lp-sk.dts
> 
> Is this coming in from v6.6-rc1 if so document that in commit message.
> 
> [...]
> 
>> diff --git a/arch/arm/dts/k3-am62-r5-lp-sk.dts b/arch/arm/dts/k3-am62-r5-lp-sk.dts
>> new file mode 100644
>> index 0000000000..ed2c028bad
>> --- /dev/null
>> +++ b/arch/arm/dts/k3-am62-r5-lp-sk.dts
>> @@ -0,0 +1,21 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * AM62x LP SK dts file for R5 SPL
>> + * Copyright (C) 2021-2023 Texas Instruments Incorporated - https://www.ti.com/
>> + */
>> +
>> +#include "k3-am62-lp-sk.dts"
>> +#include "k3-am62x-ddr-lp4-50-800-800.dtsi"
>> +#include "k3-am62-ddr.dtsi"
>> +
>> +#include "k3-am62-lp-sk-u-boot.dtsi"
>> +#include "k3-am62x-r5-sk-common.dtsi"
>> +
>> +/ {
>> +	memory at 80000000 {
>> +		device_type = "memory";
>> +		/* 2G RAM */
>> +		reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
>> +		bootph-pre-ram;
>> +	};
>> +};
> 
> NAK. should come from board.dts.
> 
>> diff --git a/arch/arm/dts/k3-am62x-ddr-lp4-50-800-800.dtsi b/arch/arm/dts/k3-am62x-ddr-lp4-50-800-800.dtsi
>> new file mode 100644
>> index 0000000000..74693d12e1
>> --- /dev/null
>> +++ b/arch/arm/dts/k3-am62x-ddr-lp4-50-800-800.dtsi
>> @@ -0,0 +1,2190 @@
>> +// SPDX-License-Identifier: GPL-2.0+
>> +/*
>> + * This file was generated with the
>> + * AM62x SysConfig DDR Subsystem Register Configuration Tool v0.08.61
>> + * Tue Mar 22 2022 17:03:08 GMT-0500 (Central Daylight Time)
> 
> Are you sure this does'nt need a sync up to latest?
> 
>> + * DDR Type: LPDDR4
> 
> Would be good to document the exact DDR part.
> 
>> + * F0 = 50MHz    F1 = 800MHz    F2 = 800MHz
>> + * Density (per channel): 16Gb
>> + * Number of Ranks: 1
>> + */
>> +
> 
> 	[...]
> 

-- 
Regards,
Nitin