[PATCH 2/3] board: rockchip: Add Maskrom Mode for Anbernic RGxx3
Chris Morgan
macromorgan at hotmail.com
Wed Oct 25 21:15:57 CEST 2023
On Mon, Oct 23, 2023 at 07:12:14PM +0200, Jonas Karlman wrote:
> Hi Chris,
>
> On 2023-10-23 17:18, Chris Morgan wrote:
> > On Mon, Oct 23, 2023 at 06:10:07PM +0800, Kever Yang wrote:
> >> Hi Chris,
> >>
> >> On 2023/10/18 02:24, Chris Morgan wrote:
> >>> From: Chris Morgan <macromorgan at hotmail.com>
> >>>
> >>> Add support for users to enter maskrom mode by holding the function
> >>> button when they power up the device.
> >>>
> >>> Since the device has soldered eMMC and sometimes does not expose a clk
> >>> pin on the mainboard
> >>
> >> This board already available, so does this clk pin available?
> >>
> >> Not only clk, other cmd/data pin is also OK to make the soc get into maskrom
> >> mode.
> >
> > No, as near as I can tell some boards (such as the 353P and 353V) don't
> > expose a clk, cmd, or data pin. The 353M does expose a clk pin though.
> >
> >>
> >>> there is a small chance that a user who flashes a
> >>> bad bootloader may not be able to recover if the headers themselves
> >>> are valid. As a result this check is done during spl_early_init() to
> >>> ensure that it runs as early as possible, and it does so by directly
> >>> manipulating the ADC hardware in lieu of loading the ADC driver.
> >>
> >> This key seems like a "recovery" adc key instead of "maskrom" key, right?
> >>
> >> I think we don't need to add this patch if the hardware does not really have
> >> a "maskrom" key.
> >>
> >> Basically the "maskrom" key should not depends on any software.
> >
> > Okay, so should I rename it as a "recovery" key? Basically it's just
> > a button hooked up to ADC channel 0. I'm trying to make as simple a
> > failsafe as possible, because for the boards without the clk/cmd pads
> > I want to make it easy to debrick in the event of something like a
> > bad U-Boot stage or a bad A-TF stage.
>
> Isn't this very similar to what arch/arm/mach-rockchip/boot_mode.c and
> rockchip_dnl_key_pressed() already does, or is supposed to do?
>
> Maybe this existing code can be changed/fixed to work earlier in SPL and
> possible also read recovery button information from DT or Kconfig to
> work with more rockchip boards?
>
> Would be nice if a hang/panic in SPL make rk devices reset into maskrom
> usb mode. Maybe even the watchdog can be of some use here.
>
> Btw, you could probably also enable CONFIG_SPL_FIT_SIGNATURE for added
> protection against starting corrupt/bitrot FIT images. To speed up boot
> after adding a sha256 checksum test, you can use following rfc/patch:
>
> [RFC] rockchip: spl: Enable caches to speed up checksum validation
> https://patchwork.ozlabs.org/patch/1802303/
>
> Regards,
> Jonas
Thank you, yes I will look into that. That said even if we detect a
corrupt SPL stage we're still stuck unless we add the additional
reset stuff like you mention.
Yes, this is more or less identical to the rockchip_dnl_key_pressed()
function with 2 distinct differences; one this doesn't require the ADC
driver since we're manipulating the controller directly (this makes it
easier to support in SPL or maybe even one day TPL), and two the
existing function has hard-coded checks for channel 1 whereas the board
here uses channel 0 for the function button. The comments for the
existing function suggest that it's meant to be "generic" and boards
are welcome to override with their own function, which is what I'm
doing though at an earlier stage in the boot process.
Thank you,
Chris
>
> >
> > Thank you.
> >
> >>
> >>
> >> Thanks,
> >>
> >> - Kever
> >>
> >>>
> >>> Ideally, once we have an open source TPL stage we can move this to
> >>> the TPL stage, so it will run even earlier.
> >>>
> >>> Signed-off-by: Chris Morgan <macromorgan at hotmail.com>
> >>> ---
> >>> board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c | 64 ++++++++++++++++++++++
> >>> 1 file changed, 64 insertions(+)
> >>>
> >>> diff --git a/board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c b/board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c
> >>> index 3d0c614623..a93b11cd47 100644
> >>> --- a/board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c
> >>> +++ b/board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c
> >>> @@ -6,12 +6,14 @@
> >>> #include <abuf.h>
> >>> #include <adc.h>
> >>> #include <asm/io.h>
> >>> +#include <command.h>
> >>> #include <display.h>
> >>> #include <dm.h>
> >>> #include <dm/lists.h>
> >>> #include <env.h>
> >>> #include <fdt_support.h>
> >>> #include <linux/delay.h>
> >>> +#include <linux/iopoll.h>
> >>> #include <mipi_dsi.h>
> >>> #include <mmc.h>
> >>> #include <panel.h>
> >>> @@ -20,6 +22,8 @@
> >>> #include <stdlib.h>
> >>> #include <video_bridge.h>
> >>> +#define BOOT_BROM_DOWNLOAD 0xef08a53c
> >>> +
> >>> #define GPIO0_BASE 0xfdd60000
> >>> #define GPIO4_BASE 0xfe770000
> >>> #define GPIO_SWPORT_DR_L 0x0000
> >>> @@ -33,6 +37,14 @@
> >>> #define GPIO_WRITEMASK(bits) ((bits) << 16)
> >>> +#define SARADC_BASE 0xfe720000
> >>> +#define SARADC_DATA 0x0000
> >>> +#define SARADC_STAS 0x0004
> >>> +#define SARADC_ADC_STATUS BIT(0)
> >>> +#define SARADC_CTRL 0x0008
> >>> +#define SARADC_INPUT_SRC_MSK 0x7
> >>> +#define SARADC_POWER_CTRL BIT(3)
> >>> +
> >>> #define DTB_DIR "rockchip/"
> >>> struct rg3xx_model {
> >>> @@ -118,12 +130,64 @@ static const struct rg353_panel rg353_panel_details[] = {
> >>> },
> >>> };
> >>> +/*
> >>> + * The device has internal eMMC, and while some devices have an exposed
> >>> + * clk pin you can ground to force a bypass not all devices do. As a
> >>> + * result it may be possible for some devices to become a perma-brick
> >>> + * if a corrupted TPL or SPL stage with a valid header is flashed to
> >>> + * the internal eMMC. Add functionality to read ADC channel 0 (the func
> >>> + * button) as early as possible in the boot process to provide some
> >>> + * protection against this. If we ever get an open TPL stage, we should
> >>> + * consider moving this function there.
> >>> + */
> >>> +void read_func_button(void)
> >>> +{
> >>> + int ret;
> >>> + u32 reg;
> >>> +
> >>> + /* Turn off SARADC to reset it. */
> >>> + writel(0, (SARADC_BASE + SARADC_CTRL));
> >>> +
> >>> + /* Enable channel 0 and power on SARADC. */
> >>> + writel(((0 & SARADC_INPUT_SRC_MSK) | SARADC_POWER_CTRL),
> >>> + (SARADC_BASE + SARADC_CTRL));
> >>> +
> >>> + /*
> >>> + * Wait for data to be ready. Use timeout of 20000us from
> >>> + * rockchip_saradc driver.
> >>> + */
> >>> + ret = readl_poll_timeout((SARADC_BASE + SARADC_STAS), reg,
> >>> + !(reg & SARADC_ADC_STATUS), 20000);
> >>> + if (ret) {
> >>> + printf("ADC Timeout");
> >>> + return;
> >>> + }
> >>> +
> >>> + /* Read the data from the SARADC. */
> >>> + reg = readl((SARADC_BASE + SARADC_DATA));
> >>> +
> >>> + /* Turn the SARADC back off so it's ready to be used again. */
> >>> + writel(0, (SARADC_BASE + SARADC_CTRL));
> >>> +
> >>> + /*
> >>> + * If the value is less than 30 the button is being pressed.
> >>> + * Reset the device back into Rockchip download mode.
> >>> + */
> >>> + if (reg <= 30) {
> >>> + printf("download key pressed, entering download mode...");
> >>> + writel(BOOT_BROM_DOWNLOAD, CONFIG_ROCKCHIP_BOOT_MODE_REG);
> >>> + do_reset(NULL, 0, 0, NULL);
> >>> + }
> >>> +};
> >>> +
> >>> /*
> >>> * Start LED very early so user knows device is on. Set color
> >>> * to red.
> >>> */
> >>> void spl_board_init(void)
> >>> {
> >>> + read_func_button();
> >>> +
> >>> /* Set GPIO0_C5, GPIO0_C6, and GPIO0_C7 to output. */
> >>> writel(GPIO_WRITEMASK(GPIO_C7 | GPIO_C6 | GPIO_C5) | \
> >>> (GPIO_C7 | GPIO_C6 | GPIO_C5),
>
More information about the U-Boot
mailing list