[PATCH 7/8] clk/qcom: add mnd_width to clk_rcg_set_rate_mnd()
Sumit Garg
sumit.garg at linaro.org
Fri Oct 27 13:46:04 CEST 2023
On Wed, 25 Oct 2023 at 01:55, Caleb Connolly <caleb.connolly at linaro.org> wrote:
>
> This property is needed on some platforms to ensure that only the
> relevant bits are set in the M/N/D registers.
>
> Signed-off-by: Caleb Connolly <caleb.connolly at linaro.org>
> ---
> drivers/clk/qcom/clock-apq8016.c | 4 ++--
> drivers/clk/qcom/clock-apq8096.c | 4 ++--
> drivers/clk/qcom/clock-qcom.c | 11 +++++++----
> drivers/clk/qcom/clock-qcom.h | 2 +-
> drivers/clk/qcom/clock-qcs404.c | 20 ++++++++++----------
> drivers/clk/qcom/clock-sdm845.c | 3 +--
> 6 files changed, 23 insertions(+), 21 deletions(-)
>
Reviewed-by: Sumit Garg <sumit.garg at linaro.org>
-Sumit
> diff --git a/drivers/clk/qcom/clock-apq8016.c b/drivers/clk/qcom/clock-apq8016.c
> index f74f7a0f5ad9..5eba18739cfb 100644
> --- a/drivers/clk/qcom/clock-apq8016.c
> +++ b/drivers/clk/qcom/clock-apq8016.c
> @@ -61,7 +61,7 @@ static int clk_init_sdc(struct qcom_cc_priv *priv, int slot, uint rate)
> clk_enable_cbc(priv->base + SDCC_AHB_CBCR(slot));
> /* 800Mhz/div, gpll0 */
> clk_rcg_set_rate_mnd(priv->base, &sdc_regs[slot], div, 0, 0,
> - CFG_CLK_SRC_GPLL0);
> + CFG_CLK_SRC_GPLL0, 8);
> clk_enable_gpll0(priv->base, &gpll0_vote_clk);
> clk_enable_cbc(priv->base + SDCC_APPS_CBCR(slot));
>
> @@ -84,7 +84,7 @@ static int clk_init_uart(struct qcom_cc_priv *priv)
>
> /* 7372800 uart block clock @ GPLL0 */
> clk_rcg_set_rate_mnd(priv->base, &uart2_regs, 1, 144, 15625,
> - CFG_CLK_SRC_GPLL0);
> + CFG_CLK_SRC_GPLL0, 8);
>
> /* Vote for gpll0 clock */
> clk_enable_gpll0(priv->base, &gpll0_vote_clk);
> diff --git a/drivers/clk/qcom/clock-apq8096.c b/drivers/clk/qcom/clock-apq8096.c
> index 1efb6e2313a5..48cac08eed67 100644
> --- a/drivers/clk/qcom/clock-apq8096.c
> +++ b/drivers/clk/qcom/clock-apq8096.c
> @@ -48,7 +48,7 @@ static int clk_init_sdc(struct qcom_cc_priv *priv, uint rate)
>
> clk_enable_cbc(priv->base + SDCC2_AHB_CBCR);
> clk_rcg_set_rate_mnd(priv->base, &sdc_regs, div, 0, 0,
> - CFG_CLK_SRC_GPLL0);
> + CFG_CLK_SRC_GPLL0, 8);
> clk_enable_gpll0(priv->base, &gpll0_vote_clk);
> clk_enable_cbc(priv->base + SDCC2_APPS_CBCR);
>
> @@ -70,7 +70,7 @@ static int clk_init_uart(struct qcom_cc_priv *priv)
>
> /* 7372800 uart block clock @ GPLL0 */
> clk_rcg_set_rate_mnd(priv->base, &uart2_regs, 1, 192, 15625,
> - CFG_CLK_SRC_GPLL0);
> + CFG_CLK_SRC_GPLL0, 8);
>
> /* Vote for gpll0 clock */
> clk_enable_gpll0(priv->base, &gpll0_vote_clk);
> diff --git a/drivers/clk/qcom/clock-qcom.c b/drivers/clk/qcom/clock-qcom.c
> index a9602d0c9ca6..7a6157bf123f 100644
> --- a/drivers/clk/qcom/clock-qcom.c
> +++ b/drivers/clk/qcom/clock-qcom.c
> @@ -83,7 +83,7 @@ void clk_bcr_update(phys_addr_t apps_cmd_rcgr)
>
> /* root set rate for clocks with half integer and MND divider */
> void clk_rcg_set_rate_mnd(phys_addr_t base, const struct bcr_regs *regs,
> - int div, int m, int n, int source)
> + int div, int m, int n, int source, u8 mnd_width)
> {
> u32 cfg;
> /* M value for MND divider. */
> @@ -92,11 +92,14 @@ void clk_rcg_set_rate_mnd(phys_addr_t base, const struct bcr_regs *regs,
> u32 n_val = ~((n) - (m)) * !!(n);
> /* NOT 2D value for MND divider. */
> u32 d_val = ~(n);
> + u32 mask = BIT(mnd_width) - 1;
> +
> + debug("m %#x n %#x d %#x div %#x mask %#x\n", m_val, n_val, d_val, div, mask);
>
> /* Program MND values */
> - writel(m_val, base + regs->M);
> - writel(n_val, base + regs->N);
> - writel(d_val, base + regs->D);
> + setbits_le32(base + regs->M, m_val & mask);
> + setbits_le32(base + regs->N, n_val & mask);
> + setbits_le32(base + regs->D, d_val & mask);
>
> /* setup src select and divider */
> cfg = readl(base + regs->cfg_rcgr);
> diff --git a/drivers/clk/qcom/clock-qcom.h b/drivers/clk/qcom/clock-qcom.h
> index 4c5959b60038..6fa88fb40af8 100644
> --- a/drivers/clk/qcom/clock-qcom.h
> +++ b/drivers/clk/qcom/clock-qcom.h
> @@ -70,7 +70,7 @@ void clk_bcr_update(phys_addr_t apps_cmd_rgcr);
> void clk_enable_cbc(phys_addr_t cbcr);
> void clk_enable_vote_clk(phys_addr_t base, const struct vote_clk *vclk);
> void clk_rcg_set_rate_mnd(phys_addr_t base, const struct bcr_regs *regs,
> - int div, int m, int n, int source);
> + int div, int m, int n, int source, u8 mnd_width);
> void clk_rcg_set_rate(phys_addr_t base, const struct bcr_regs *regs, int div,
> int source);
>
> diff --git a/drivers/clk/qcom/clock-qcs404.c b/drivers/clk/qcom/clock-qcs404.c
> index ce83ec741278..d10992ee58bf 100644
> --- a/drivers/clk/qcom/clock-qcs404.c
> +++ b/drivers/clk/qcom/clock-qcs404.c
> @@ -113,7 +113,7 @@ static const struct bcr_regs blsp1_qup4_i2c_apps_regs = {
> /* mnd_width = 0 */
> };
>
> -ulong msm_set_rate(struct clk *clk, ulong rate)
> +static ulong qcs404_set_rate(struct clk *clk, ulong rate)
> {
> struct qcom_cc_priv *priv = dev_get_priv(clk->dev);
>
> @@ -121,7 +121,7 @@ ulong msm_set_rate(struct clk *clk, ulong rate)
> case GCC_BLSP1_UART2_APPS_CLK:
> /* UART: 115200 */
> clk_rcg_set_rate_mnd(priv->base, &uart2_regs, 0, 12, 125,
> - CFG_CLK_SRC_CXO);
> + CFG_CLK_SRC_CXO, 8);
> clk_enable_cbc(priv->base + BLSP1_UART2_APPS_CBCR);
> break;
> case GCC_BLSP1_AHB_CLK:
> @@ -130,7 +130,7 @@ ulong msm_set_rate(struct clk *clk, ulong rate)
> case GCC_SDCC1_APPS_CLK:
> /* SDCC1: 200MHz */
> clk_rcg_set_rate_mnd(priv->base, &sdc_regs, 4, 0, 0,
> - CFG_CLK_SRC_GPLL0);
> + CFG_CLK_SRC_GPLL0, 8);
> clk_enable_gpll0(priv->base, &gpll0_vote_clk);
> clk_enable_cbc(priv->base + SDCC_APPS_CBCR(1));
> break;
> @@ -140,16 +140,16 @@ ulong msm_set_rate(struct clk *clk, ulong rate)
> case GCC_ETH_RGMII_CLK:
> if (rate == 250000000)
> clk_rcg_set_rate_mnd(priv->base, &emac_regs, 2, 0, 0,
> - CFG_CLK_SRC_GPLL1);
> + CFG_CLK_SRC_GPLL1, 8);
> else if (rate == 125000000)
> clk_rcg_set_rate_mnd(priv->base, &emac_regs, 4, 0, 0,
> - CFG_CLK_SRC_GPLL1);
> + CFG_CLK_SRC_GPLL1, 8);
> else if (rate == 50000000)
> clk_rcg_set_rate_mnd(priv->base, &emac_regs, 10, 0, 0,
> - CFG_CLK_SRC_GPLL1);
> + CFG_CLK_SRC_GPLL1, 8);
> else if (rate == 5000000)
> clk_rcg_set_rate_mnd(priv->base, &emac_regs, 2, 1, 50,
> - CFG_CLK_SRC_GPLL1);
> + CFG_CLK_SRC_GPLL1, 8);
> break;
> default:
> return 0;
> @@ -166,7 +166,7 @@ static int qcs404_enable(struct clk *clk)
> case GCC_USB30_MASTER_CLK:
> clk_enable_cbc(priv->base + USB30_MASTER_CBCR);
> clk_rcg_set_rate_mnd(priv->base, &usb30_master_regs, 4, 0, 0,
> - CFG_CLK_SRC_GPLL0);
> + CFG_CLK_SRC_GPLL0, 8);
> break;
> case GCC_SYS_NOC_USB3_CLK:
> clk_enable_cbc(priv->base + SYS_NOC_USB3_CBCR);
> @@ -188,14 +188,14 @@ static int qcs404_enable(struct clk *clk)
> clk_enable_cbc(priv->base + ETH_PTP_CBCR);
> clk_enable_gpll0(priv->base, &gpll1_vote_clk);
> clk_rcg_set_rate_mnd(priv->base, &emac_ptp_regs, 2, 0, 0,
> - CFG_CLK_SRC_GPLL1);
> + CFG_CLK_SRC_GPLL1, 8);
> break;
> case GCC_ETH_RGMII_CLK:
> /* SPEED_1000: freq -> 250MHz */
> clk_enable_cbc(priv->base + ETH_RGMII_CBCR);
> clk_enable_gpll0(priv->base, &gpll1_vote_clk);
> clk_rcg_set_rate_mnd(priv->base, &emac_regs, 2, 0, 0,
> - CFG_CLK_SRC_GPLL1);
> + CFG_CLK_SRC_GPLL1, 8);
> break;
> case GCC_ETH_SLAVE_AHB_CLK:
> clk_enable_cbc(priv->base + ETH_SLAVE_AHB_CBCR);
> diff --git a/drivers/clk/qcom/clock-sdm845.c b/drivers/clk/qcom/clock-sdm845.c
> index 7b614f9661f0..9345d5293f1e 100644
> --- a/drivers/clk/qcom/clock-sdm845.c
> +++ b/drivers/clk/qcom/clock-sdm845.c
> @@ -82,8 +82,7 @@ static ulong sdm845_set_rate(struct clk *clk, ulong rate)
> case GCC_QUPV3_WRAP1_S1_CLK: /* UART9 */
> freq = qcom_find_freq(ftbl_gcc_qupv3_wrap0_s0_clk_src, rate);
> clk_rcg_set_rate_mnd(priv->base, &uart2_regs,
> - freq->pre_div, freq->m, freq->n, freq->src);
> -
> + freq->pre_div, freq->m, freq->n, freq->src, 16);
> return freq->freq;
> default:
> return 0;
>
> --
> 2.42.0
>
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