[resend v2 03/19] include: asm: Add support to read/write 64-bit

dinesh.maniyam at intel.com dinesh.maniyam at intel.com
Thu Dec 5 10:22:59 CET 2024


From: Dinesh Maniyam <dinesh.maniyam at intel.com>

Extend support read and write 64-bits of buffer.
This is required for Cadence NAND Driver to
read/write ONFI parameter page. The parameter page is mapped to 64-bit.
With only read/write 32 bits of buffer,there is an issue of overwriting
last 4 bits of buffer which failed the NAND identification.

Signed-off-by: Dinesh Maniyam <dinesh.maniyam at intel.com>

---
v2:
- remove the "this patch is to" commit phrases
---
---
 arch/arm/include/asm/io.h | 25 +++++++++++++++++++++++++
 1 file changed, 25 insertions(+)

diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
index 89b1015bc4..e3ea5f0eb2 100644
--- a/arch/arm/include/asm/io.h
+++ b/arch/arm/include/asm/io.h
@@ -391,6 +391,31 @@ void __memset_io(volatile void __iomem *dst, int c, size_t count)
 		count--;
 	}
 }
+
+static inline void readsq(const void __iomem *addr, void *buffer,
+			  unsigned int count)
+{
+	if (count) {
+		u64 *buf = buffer;
+
+		do {
+			u64 x = __raw_readq(addr);
+			*buf++ = x;
+		} while (--count);
+	}
+}
+
+static inline void writesq(void __iomem *addr, const void *buffer,
+			   unsigned int count)
+{
+	if (count) {
+		const u64 *buf = buffer;
+
+		do {
+			__raw_writeq(*buf++, addr);
+		} while (--count);
+	}
+}
 #endif /* CONFIG_ARM64 */
 
 #ifdef CONFIG_ARM64
-- 
2.19.0



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