[PATCH] arm64: zynqmp: Sync with v6.12 kernel
Michal Simek
michal.simek at amd.com
Thu Dec 5 14:29:32 CET 2024
On 11/28/24 15:49, Michal Simek wrote:
> Sync zynqmp* DTS files with v6.12 Linux kernel.
>
> Signed-off-by: Michal Simek <michal.simek at amd.com>
> ---
>
> Hope that we get soon to be able to enable OF_UPSTREAM instead.
> ---
> arch/arm/dts/zynqmp-clk-ccf.dtsi | 16 ++++++++++
> arch/arm/dts/zynqmp-sm-k26-revA.dts | 2 +-
> arch/arm/dts/zynqmp-smk-k26-revA.dts | 2 +-
> arch/arm/dts/zynqmp-zcu102-revA.dts | 1 +
> arch/arm/dts/zynqmp-zcu1275-revA.dts | 3 +-
> arch/arm/dts/zynqmp.dtsi | 44 +++++++++++++++++++++++-----
> 6 files changed, 57 insertions(+), 11 deletions(-)
>
> diff --git a/arch/arm/dts/zynqmp-clk-ccf.dtsi b/arch/arm/dts/zynqmp-clk-ccf.dtsi
> index dd4569e7bd95..60d1b1acf9a0 100644
> --- a/arch/arm/dts/zynqmp-clk-ccf.dtsi
> +++ b/arch/arm/dts/zynqmp-clk-ccf.dtsi
> @@ -70,6 +70,22 @@
> clocks = <&zynqmp_clk ACPU>;
> };
>
> +&cpu0_debug {
> + clocks = <&zynqmp_clk DBF_FPD>;
> +};
> +
> +&cpu1_debug {
> + clocks = <&zynqmp_clk DBF_FPD>;
> +};
> +
> +&cpu2_debug {
> + clocks = <&zynqmp_clk DBF_FPD>;
> +};
> +
> +&cpu3_debug {
> + clocks = <&zynqmp_clk DBF_FPD>;
> +};
> +
> &fpd_dma_chan1 {
> clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
> };
> diff --git a/arch/arm/dts/zynqmp-sm-k26-revA.dts b/arch/arm/dts/zynqmp-sm-k26-revA.dts
> index 8c43ade94053..620f5185cc46 100644
> --- a/arch/arm/dts/zynqmp-sm-k26-revA.dts
> +++ b/arch/arm/dts/zynqmp-sm-k26-revA.dts
> @@ -3,7 +3,7 @@
> * dts file for Xilinx ZynqMP SM-K26 rev2/1/B/A
> *
> * (C) Copyright 2020 - 2021, Xilinx, Inc.
> - * (C) Copyright 2023, Advanced Micro Devices, Inc.
> + * (C) Copyright 2023 - 2024, Advanced Micro Devices, Inc.
> *
> * Michal Simek <michal.simek at amd.com>
> */
> diff --git a/arch/arm/dts/zynqmp-smk-k26-revA.dts b/arch/arm/dts/zynqmp-smk-k26-revA.dts
> index 719a4e49b574..b804abe89d1d 100644
> --- a/arch/arm/dts/zynqmp-smk-k26-revA.dts
> +++ b/arch/arm/dts/zynqmp-smk-k26-revA.dts
> @@ -3,7 +3,7 @@
> * dts file for Xilinx ZynqMP SMK-K26 rev2/1/B/A
> *
> * (C) Copyright 2020 - 2021, Xilinx, Inc.
> - * (C) Copyright 2023, Advanced Micro Devices, Inc.
> + * (C) Copyright 2023 - 2024, Advanced Micro Devices, Inc.
> *
> * Michal Simek <michal.simek at amd.com>
> */
> diff --git a/arch/arm/dts/zynqmp-zcu102-revA.dts b/arch/arm/dts/zynqmp-zcu102-revA.dts
> index 3132fa533b8e..dd63d22f45e7 100644
> --- a/arch/arm/dts/zynqmp-zcu102-revA.dts
> +++ b/arch/arm/dts/zynqmp-zcu102-revA.dts
> @@ -960,6 +960,7 @@
>
> &pcie {
> status = "okay";
> + phys = <&psgtr 0 PHY_TYPE_PCIE 0 0>;
> };
>
> &psgtr {
> diff --git a/arch/arm/dts/zynqmp-zcu1275-revA.dts b/arch/arm/dts/zynqmp-zcu1275-revA.dts
> index 095c972f1322..b75b2a796eb3 100644
> --- a/arch/arm/dts/zynqmp-zcu1275-revA.dts
> +++ b/arch/arm/dts/zynqmp-zcu1275-revA.dts
> @@ -15,8 +15,7 @@
>
> / {
> model = "ZynqMP ZCU1275 RevA";
> - compatible = "xlnx,zynqmp-zcu1275-revA", "xlnx,zynqmp-zcu1275",
> - "xlnx,zynqmp";
> + compatible = "xlnx,zynqmp-zcu1275-revA", "xlnx,zynqmp-zcu1275", "xlnx,zynqmp";
>
> aliases {
> serial0 = &uart0;
> diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi
> index 6a29f6101534..70ca5e6379fc 100644
> --- a/arch/arm/dts/zynqmp.dtsi
> +++ b/arch/arm/dts/zynqmp.dtsi
> @@ -168,8 +168,8 @@
> bootph-all;
> };
>
> - pmu: pmu {
> - compatible = "arm,armv8-pmuv3";
> + pmu {
> + compatible = "arm,cortex-a53-pmu";
> interrupt-parent = <&gic>;
> interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
> @@ -441,6 +441,34 @@
> };
> };
>
> + cpu0_debug: debug at fec10000 {
> + compatible = "arm,coresight-cpu-debug", "arm,primecell";
> + reg = <0x0 0xfec10000 0x0 0x1000>;
> + clock-names = "apb_pclk";
> + cpu = <&cpu0>;
> + };
> +
> + cpu1_debug: debug at fed10000 {
> + compatible = "arm,coresight-cpu-debug", "arm,primecell";
> + reg = <0x0 0xfed10000 0x0 0x1000>;
> + clock-names = "apb_pclk";
> + cpu = <&cpu1>;
> + };
> +
> + cpu2_debug: debug at fee10000 {
> + compatible = "arm,coresight-cpu-debug", "arm,primecell";
> + reg = <0x0 0xfee10000 0x0 0x1000>;
> + clock-names = "apb_pclk";
> + cpu = <&cpu2>;
> + };
> +
> + cpu3_debug: debug at fef10000 {
> + compatible = "arm,coresight-cpu-debug", "arm,primecell";
> + reg = <0x0 0xfef10000 0x0 0x1000>;
> + clock-names = "apb_pclk";
> + cpu = <&cpu3>;
> + };
> +
> /* GDMA */
> fpd_dma_chan1: dma-controller at fd500000 {
> status = "disabled";
> @@ -885,7 +913,6 @@
> power-domains = <&zynqmp_firmware PD_SATA>;
> resets = <&zynqmp_reset ZYNQMP_RESET_SATA>;
> /* iommus = <&smmu 0x4c0>, <&smmu 0x4c1>, <&smmu 0x4c2>, <&smmu 0x4c3>; */
> - /* dma-coherent; */
> };
>
> sdhci0: mmc at ff160000 {
> @@ -1065,9 +1092,9 @@
> <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
> + clock-names = "ref";
> /* iommus = <&smmu 0x860>; */
> snps,quirk-frame-length-adjustment = <0x20>;
> - clock-names = "ref";
> snps,resume-hs-terminations;
> /* dma-coherent; */
> };
> @@ -1097,9 +1124,9 @@
> <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
> + clock-names = "ref";
> /* iommus = <&smmu 0x861>; */
> snps,quirk-frame-length-adjustment = <0x20>;
> - clock-names = "ref";
> snps,resume-hs-terminations;
> /* dma-coherent; */
> };
> @@ -1176,11 +1203,14 @@
> "dp_vtc_pixel_clk_in";
> power-domains = <&zynqmp_firmware PD_DP>;
> resets = <&zynqmp_reset ZYNQMP_RESET_DP>;
> - dma-names = "vid0", "vid1", "vid2", "gfx0";
> + dma-names = "vid0", "vid1", "vid2", "gfx0",
> + "aud0", "aud1";
> dmas = <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO0>,
> <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO1>,
> <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO2>,
> - <&zynqmp_dpdma ZYNQMP_DPDMA_GRAPHICS>;
> + <&zynqmp_dpdma ZYNQMP_DPDMA_GRAPHICS>,
> + <&zynqmp_dpdma ZYNQMP_DPDMA_AUDIO0>,
> + <&zynqmp_dpdma ZYNQMP_DPDMA_AUDIO1>;
>
> ports {
> #address-cells = <1>;
This patch has been already applied to Tom's next branch.
Thanks,
Michal
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