[PATCH v7 02/12] riscv: dts: jh7110: Make u-boot device trees adapting to upstream DT

[Hal Feng]

> On 05.12.24 03:07, E Shattow wrote:
> On Mon, Dec 2, 2024 at 7:05 PM Hal Feng <hal.feng at starfivetech.com>
> wrote:
> >
> > Add u-boot features to the U-Boot device tree.
> >
> > Tested-by: Anand Moon <linux.amoon at gmail.com>
> > Tested-by: E Shattow <lucent at gmail.com>
> > Reviewed-by: E Shattow <lucent at gmail.com>
> > Acked-by: Sumit Garg <sumit.garg at linaro.org>
> > Signed-off-by: Hal Feng <hal.feng at starfivetech.com>
> > ---
> >  ...10-starfive-visionfive-2-v1.3b-u-boot.dtsi | 33 +++++++++++++++---
> >  arch/riscv/dts/jh7110-u-boot.dtsi             | 34 +++++++++++++++++++
> >  2 files changed, 63 insertions(+), 4 deletions(-)
> >
> > diff --git
> > a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi
> > b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi
> > index 3012466b30..7953459e67 100644
> > --- a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi
> > +++ b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi
> > @@ -6,6 +6,10 @@
> >  #include "binman.dtsi"
> >  #include "jh7110-u-boot.dtsi"
> >  / {
> > +       aliases {
> > +               spi0 = &qspi;
> > +       };
> > +
> >         chosen {
> >                 bootph-pre-ram;
> >         };
> > @@ -27,6 +31,9 @@
> >
> >  &uart0 {
> >         bootph-pre-ram;
> > +       reg-offset = <0>;
> > +       current-speed = <115200>;
> > +       clock-frequency = <24000000>;
> >  };
> >
> >  &mmc0 {
> > @@ -39,30 +46,45 @@
> >
> >  &qspi {
> >         bootph-pre-ram;
> > +       spi-max-frequency = <250000000>;
> >
> > -       nor-flash at 0 {
> > +       flash at 0 {
> >                 bootph-pre-ram;
> > +               /delete-property/ cdns,read-delay;
> > +               spi-max-frequency = <100000000>;
> >         };
> >  };
> >
> > +&syscrg {
> > +       assigned-clocks = <&syscrg JH7110_SYSCLK_CPU_ROOT>,
> > +                         <&syscrg JH7110_SYSCLK_BUS_ROOT>,
> > +                         <&syscrg JH7110_SYSCLK_PERH_ROOT>,
> > +                         <&syscrg JH7110_SYSCLK_QSPI_REF>;
> > +       assigned-clock-parents = <&pllclk JH7110_PLLCLK_PLL0_OUT>,
> > +                                <&pllclk JH7110_PLLCLK_PLL2_OUT>,
> > +                                <&pllclk JH7110_PLLCLK_PLL2_OUT>,
> > +                                <&syscrg JH7110_SYSCLK_QSPI_REF_SRC>;
> > +       assigned-clock-rates = <0>, <0>, <0>, <0>; };
> > +
> >  &sysgpio {
> >         bootph-pre-ram;
> >  };
> >
> >  &mmc0_pins {
> >         bootph-pre-ram;
> > -       mmc0-pins-rest {
> > +       rst-pins {
> >                 bootph-pre-ram;
> >         };
> >  };
> >
> >  &mmc1_pins {
> >         bootph-pre-ram;
> > -       mmc1-pins0 {
> > +       clk-pins {
> >                 bootph-pre-ram;
> >         };
> >
> > -       mmc1-pins1 {
> > +       mmc-pins {
> >                 bootph-pre-ram;
> >         };
> >  };
> > @@ -78,6 +100,9 @@
> >         bootph-pre-ram;
> >         eeprom at 50 {
> >                 bootph-pre-ram;
> > +               compatible = "atmel,24c04";
> > +               reg = <0x50>;
> > +               pagesize = <16>;
> >         };
> >  };
> >
> > diff --git a/arch/riscv/dts/jh7110-u-boot.dtsi
> > b/arch/riscv/dts/jh7110-u-boot.dtsi
> > index 52c1d60859..21a2ab1789 100644
> > --- a/arch/riscv/dts/jh7110-u-boot.dtsi
> > +++ b/arch/riscv/dts/jh7110-u-boot.dtsi
> > @@ -46,6 +46,15 @@
> >                 };
> >         };
> >
> > +       timer {
> > +               compatible = "riscv,timer";
> > +               interrupts-extended = <&cpu0_intc 5>,
> > +                                     <&cpu1_intc 5>,
> > +                                     <&cpu2_intc 5>,
> > +                                     <&cpu3_intc 5>,
> > +                                     <&cpu4_intc 5>;
> > +       };
> > +
> >         soc {
> >                 bootph-pre-ram;
> >
> > @@ -73,10 +82,35 @@
> >         bootph-pre-ram;
> >  };
> >
> > +&gmac0_rgmii_rxin {
> > +       bootph-pre-ram;
> > +};
> > +
> >  &gmac0_rmii_refin {
> >         bootph-pre-ram;
> >  };
> >
> > +&gmac1_rgmii_rxin {
> > +       bootph-pre-ram;
> > +};
> > +
> > +&gmac1_rmii_refin {
> > +       bootph-pre-ram;
> > +};
> > +
> 
> > +&stmmac_axi_setup {
> > +       snps,wr_osr_lmt = <4>;
> > +       snps,rd_osr_lmt = <4>;
> > +};
> > +
> > +&gmac0 {
> > +       snps,perfect-filter-entries = <8>; };
> > +
> > +&gmac1 {
> > +       snps,perfect-filter-entries = <8>; };
> > +
> 
> Redundant &stmmac_axi_setup &gmac0 &gmac1 property overrides
> (upstream has all these). Drop.

OK. Actually these properties are unused in U-Boot.

> 
> >  &aoncrg {
> >         bootph-pre-ram;
> >  };
> > --
> > 2.43.2
> >
> 
> There's also a redundant &S7_0 { status = "okay"; }; which can be dropped, it
> is no-op since that alias is already set to be status="okay".

OK. Drop it.

> 
> I tested on Star64 network function and cold boot, is fine. What remains are
> the liberal use of bootph-pre-ram properties, the DRAM Memory Controller
> dmc which does not appear yet in Linux, the timer {} node; elsewhere the
> eeprom and uart of which the eeprom and bootph-pre-ram properties can
> probably get upstream easily enough later on.
> 
> Your choice if you want to trim these redundant properties here or if it should
> be done as a later clean-up patch, as upstream does not have the same values
> for these properties all.

I prefer to send a clean-up patch after some changes like qspi and eeprom are
synced to upstream Linux. Because the clean-up work is not the purpose of
this series and I will note all properties this series changes in the cover letter.

Best regards,
Hal