[PATCH 1/3] arm64: Convert core type check macros into inline functions

[Biju Das]

Hi Marek,

> -----Original Message-----
> From: Marek Vasut <marek.vasut at mailbox.org>
> Sent: 16 December 2024 11:50
> Subject: Re: [PATCH 1/3] arm64: Convert core type check macros into inline functions
> 
> On 12/16/24 9:54 AM, Biju Das wrote:
> > Hi Marek,
> >
> > Thanks for the patch.
> >
> >> -----Original Message-----
> >> From: Marek Vasut <marek.vasut+renesas at mailbox.org>
> >> Sent: 14 December 2024 22:43
> >> Subject: [PATCH 1/3] arm64: Convert core type check macros into
> >> inline functions
> >>
> >> Turn the core type check macros into inline functions to perform
> >> better type checking on them. The inline functions get optimized out
> >> in case they are not used. Indent the MIDR_PARTNUM_CORTEX_An macros
> >> in preparation for addition of future three-digit cores and use MIDR_PARTNUM_SHIFT in
> MIDR_PARTNUM_MASK to be consistent.
> >>
> >> Signed-off-by: Marek Vasut <marek.vasut+renesas at mailbox.org>
> >> ---
> >> Cc: Biju Das <biju.das.jz at bp.renesas.com>
> >> Cc: Chris Paterson <chris.paterson2 at renesas.com>
> >> Cc: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>
> >> Cc: Nobuhiro Iwamatsu <iwamatsu at nigauri.org>
> >> Cc: Paul Barker <paul.barker.ct at bp.renesas.com>
> >> Cc: Tom Rini <trini at konsulko.com>
> >> Cc: u-boot at lists.denx.de
> >> ---
> >>   arch/arm/include/asm/armv8/cpu.h | 28 +++++++++++++++++-----------
> >>   1 file changed, 17 insertions(+), 11 deletions(-)
> >>
> >> diff --git a/arch/arm/include/asm/armv8/cpu.h
> >> b/arch/arm/include/asm/armv8/cpu.h
> >> index 40d54dc85ab..aa1470bb72d 100644
> >> --- a/arch/arm/include/asm/armv8/cpu.h
> >> +++ b/arch/arm/include/asm/armv8/cpu.h
> >> @@ -3,11 +3,11 @@
> >>    * Copyright 2018 NXP
> >>    */
> >>
> >> -#define MIDR_PARTNUM_CORTEX_A35	0xD04
> >> -#define MIDR_PARTNUM_CORTEX_A53	0xD03
> >> -#define MIDR_PARTNUM_CORTEX_A72	0xD08
> >> -#define MIDR_PARTNUM_SHIFT	0x4
> >> -#define MIDR_PARTNUM_MASK	(0xFFF << 0x4)
> >> +#define MIDR_PARTNUM_CORTEX_A35		0xD04
> >> +#define MIDR_PARTNUM_CORTEX_A53		0xD03
> >> +#define MIDR_PARTNUM_CORTEX_A72		0xD08
> >> +#define MIDR_PARTNUM_SHIFT		0x4
> >> +#define MIDR_PARTNUM_MASK		(0xFFF << MIDR_PARTNUM_SHIFT)
> >>
> >>   static inline unsigned int read_midr(void)  { @@ -18,9 +18,15 @@
> >> static inline unsigned int
> >> read_midr(void)
> >>   	return val;
> >>   }
> >>
> >> -#define is_cortex_a35() (((read_midr() & MIDR_PARTNUM_MASK) >> \
> >> -			 MIDR_PARTNUM_SHIFT) == MIDR_PARTNUM_CORTEX_A35)
> >> -#define is_cortex_a53() (((read_midr() & MIDR_PARTNUM_MASK) >> \
> >> -			 MIDR_PARTNUM_SHIFT) == MIDR_PARTNUM_CORTEX_A53)
> >> -#define is_cortex_a72() (((read_midr() & MIDR_PARTNUM_MASK) >>\
> >> -			 MIDR_PARTNUM_SHIFT) == MIDR_PARTNUM_CORTEX_A72)
> >> +#define is_cortex_a(__n)					\
> >> +	static inline int is_cortex_a##__n(void)		\
> >> +	{							\
> >> +		unsigned int midr = read_midr();		\
> >
> > Maybe unsigned int midr = read_midr() & MIDR_PARTNUM_MASK, to reduce
> > one store Operation???
> The compiler will optimize the result as needed, this expansion here is for readability purpose only.

OK. If all the compilers available today is making optimization for this instruction. Then, it make sense.

Cheers,
Biju