[PATCH 2/3] arm64: Add MIDR entries for Cortex-A57 and Cortex-A76

[Peter Robinson]

On Sat, 14 Dec 2024 at 23:01, Marek Vasut <marek.vasut+renesas at mailbox.org>
wrote:

> Add MIDR entries for Cortex-A57 and Cortex-A76 cores.
> Those are used on R-Car Gen3 and Gen4 SoCs respectively.
>
> Signed-off-by: Marek Vasut <marek.vasut+renesas at mailbox.org>
>
Reviewed-by: Peter Robinson <pbrobinson at gmail.com>


> ---
> Cc: Biju Das <biju.das.jz at bp.renesas.com>
> Cc: Chris Paterson <chris.paterson2 at renesas.com>
> Cc: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>
> Cc: Nobuhiro Iwamatsu <iwamatsu at nigauri.org>
> Cc: Paul Barker <paul.barker.ct at bp.renesas.com>
> Cc: Tom Rini <trini at konsulko.com>
> Cc: u-boot at lists.denx.de
> ---
>  arch/arm/include/asm/armv8/cpu.h | 4 ++++
>  1 file changed, 4 insertions(+)
>
> diff --git a/arch/arm/include/asm/armv8/cpu.h
> b/arch/arm/include/asm/armv8/cpu.h
> index aa1470bb72d..4dbb589aab8 100644
> --- a/arch/arm/include/asm/armv8/cpu.h
> +++ b/arch/arm/include/asm/armv8/cpu.h
> @@ -5,7 +5,9 @@
>
>  #define MIDR_PARTNUM_CORTEX_A35                0xD04
>  #define MIDR_PARTNUM_CORTEX_A53                0xD03
> +#define MIDR_PARTNUM_CORTEX_A57                0xD07
>  #define MIDR_PARTNUM_CORTEX_A72                0xD08
> +#define MIDR_PARTNUM_CORTEX_A76                0xD0B
>  #define MIDR_PARTNUM_SHIFT             0x4
>  #define MIDR_PARTNUM_MASK              (0xFFF << MIDR_PARTNUM_SHIFT)
>
> @@ -29,4 +31,6 @@ static inline unsigned int read_midr(void)
>
>  is_cortex_a(35)
>  is_cortex_a(53)
> +is_cortex_a(57)
>  is_cortex_a(72)
> +is_cortex_a(76)
> --
> 2.45.2
>
>