[PATCH] net: phy: Add RGMII RX/TX delay handling to DP83822 PHY

[Marek Vasut]

The TI DP83822 does have support for configurable RGMII RX/TX clock
shift, add support for parsing DT properties which describe the RX/TX
clock shift configuration and configuration of the matching bits in
RCSR register.

The shift is only configurable on DP83822, the other PHYs supported
by this PHY driver, namely DP83825/DP83826 variants, do not implement
this functionality and the RCSR bits used to configure the clock shift
are missing from those PHYs.

The shift is configurable separately for RX and TX path. Each path can
either enable the shift or disable the shift using single bit. In case
the shift is disabled, a delay of 0ns is added to the path, otherwise
a delay of 3.5ns is added to the path.

Note that the two RCSR bits 11 and 12 have inverted logic, RCSR bit 12
enables RX internal shift when SET, while RCSR bit 11 enables TX shift
when UNSET.

Signed-off-by: Marek Vasut <marex at denx.de>
---
Cc: Joe Hershberger <joe.hershberger at ni.com>
Cc: Ramon Fried <rfried.dev at gmail.com>
Cc: Tom Rini <trini at konsulko.com>
---
 drivers/net/phy/ti_phy_init.c | 48 ++++++++++++++++++++++++++++++++++-
 1 file changed, 47 insertions(+), 1 deletion(-)

diff --git a/drivers/net/phy/ti_phy_init.c b/drivers/net/phy/ti_phy_init.c
index a0878193ac0..850c0cbec96 100644
--- a/drivers/net/phy/ti_phy_init.c
+++ b/drivers/net/phy/ti_phy_init.c
@@ -10,12 +10,58 @@
 #include <phy.h>
 #include "ti_phy_init.h"
 
+#define DP83822_DEVADDR		0x1f
+
+#define MII_DP83822_RCSR	0x17
+
+/* RCSR bits */
+#define DP83822_RX_CLK_SHIFT	BIT(12)
+#define DP83822_TX_CLK_SHIFT	BIT(11)
+
+/* DP83822 specific RGMII RX/TX delay configuration. */
+static int dp83822_config(struct phy_device *phydev)
+{
+	ofnode node = phy_get_ofnode(phydev);
+	u32 rgmii_delay = 0;
+	u32 rx_delay = 0;
+	u32 tx_delay = 0;
+	int ret;
+
+	ret = ofnode_read_u32(node, "rx-internal-delay-ps", &rx_delay);
+	if (ret) {
+		rx_delay = phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
+			   phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID;
+	}
+
+	ret = ofnode_read_u32(node, "tx-internal-delay-ps", &tx_delay);
+	if (ret) {
+		tx_delay = phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
+			   phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID;
+	}
+
+	/* Bit set means Receive path internal clock shift is ENABLED */
+	if (rx_delay)
+		rgmii_delay |= DP83822_RX_CLK_SHIFT;
+
+	/* Bit set means Transmit path internal clock shift is DISABLED */
+	if (!tx_delay)
+		rgmii_delay |= DP83822_TX_CLK_SHIFT;
+
+	ret = phy_modify_mmd(phydev, DP83822_DEVADDR, MII_DP83822_RCSR,
+			     DP83822_RX_CLK_SHIFT | DP83822_TX_CLK_SHIFT,
+			     rgmii_delay);
+	if (ret)
+		return ret;
+
+	return genphy_config_aneg(phydev);
+}
+
 U_BOOT_PHY_DRIVER(dp83822) = {
 	.name = "TI DP83822",
 	.uid = 0x2000a240,
 	.mask = 0xfffffff0,
 	.features = PHY_BASIC_FEATURES,
-	.config = &genphy_config_aneg,
+	.config = &dp83822_config,
 	.startup = &genphy_startup,
 	.shutdown = &genphy_shutdown,
 };
-- 
2.45.2