[PATCH v5] mtd: spi-nor: Fix the spi_nor_read() when config SPI_STACKED_PARALLEL is enabled

[Abbarapu, Venkatesh]

Hi Tom,

> -----Original Message-----
> From: Tom Rini <trini at konsulko.com>
> Sent: Sunday, December 29, 2024 10:06 PM
> To: Abbarapu, Venkatesh <venkatesh.abbarapu at amd.com>
> Cc: u-boot at lists.denx.de; tudor.ambarus at linaro.org; j-humphreys at ti.com;
> marex at denx.de; Simek, Michal <michal.simek at amd.com>;
> jagan at amarulasolutions.com; vigneshr at ti.com; u-kumar1 at ti.com;
> seanga2 at gmail.com; caleb.connolly at linaro.org; sjg at chromium.org;
> william.zhang at broadcom.com; stefan_b at posteo.net; quentin.schulz at cherry.de;
> Takahiro.Kuwano at infineon.com; p-mantena at ti.com; git (AMD-Xilinx)
> <git at amd.com>
> Subject: Re: [PATCH v5] mtd: spi-nor: Fix the spi_nor_read() when config
> SPI_STACKED_PARALLEL is enabled
> 
> On Sat, Dec 28, 2024 at 04:29:39AM +0000, Abbarapu, Venkatesh wrote:
> > Hi Tom,
> >
> > > -----Original Message-----
> > > From: Tom Rini <trini at konsulko.com>
> > > Sent: Friday, December 27, 2024 11:53 PM
> > > To: Abbarapu, Venkatesh <venkatesh.abbarapu at amd.com>
> > > Cc: u-boot at lists.denx.de; tudor.ambarus at linaro.org;
> > > j-humphreys at ti.com; marex at denx.de; Simek, Michal
> > > <michal.simek at amd.com>; jagan at amarulasolutions.com; vigneshr at ti.com;
> > > u-kumar1 at ti.com; seanga2 at gmail.com; caleb.connolly at linaro.org;
> > > sjg at chromium.org; william.zhang at broadcom.com; stefan_b at posteo.net;
> > > quentin.schulz at cherry.de; Takahiro.Kuwano at infineon.com;
> > > p-mantena at ti.com; git (AMD-Xilinx) <git at amd.com>
> > > Subject: Re: [PATCH v5] mtd: spi-nor: Fix the spi_nor_read() when
> > > config SPI_STACKED_PARALLEL is enabled
> > >
> > > On Fri, Dec 27, 2024 at 10:19:34AM +0530, Venkatesh Yadav Abbarapu wrote:
> > >
> > > > Update the spi_nor_read() function based on the config
> > > > SPI_FLASH_BAR and update the length and bank calculation by
> > > > spliting the memory of 16MB size banks only when the address width is 3byte.
> > > > Fix the read issue for 4byte address width by passing the entire
> > > > length to the read function. Also update the size when the
> > > > configuration is stacked.
> > > >
> > > > Fixes: 5d40b3d384 ("mtd: spi-nor: Add parallel and stacked
> > > > memories
> > > > support")
> > > > Signed-off-by: Venkatesh Yadav Abbarapu
> > > > <venkatesh.abbarapu at amd.com>
> > >
> > > I don't think you've run this through CI?
> > > https://source.denx.de/u-boot/u-boot/-/jobs/984698#L289 and similar
> > > on all sandbox targets, and Azure shows it too.
> > >
> >
> > Ok...Could you please run the CI on the "v3 patch" once, as this patch is entirely
> separated the parallel code with the default one.
> >
> > [PATCH v3] mtd: spi-nor: Fix the spi_nor_read() when config
> > SPI_STACKED_PARALLEL is enabled
> 
> Yes, v3 passes CI. Does the help with what you need to do for v6 then?

Thanks for running CI with v3. I sent v6 patch considering the v3 related changes and mostly this should pass the CI. If there are any issues seen with v6 then we need to consider v3 patch as the comment is only with the additional #ifdef statement for the parallel configuration.

Thanks
Venkatesh

> 
> --
> Tom