[PATCH 7/9] rockchip: bob: kevin: Disable dcache in SPL

[Jonas Karlman]

Hi Simon,

On 2024-06-05 05:25, Simon Glass wrote:
> This causes a hang, so disable it.

When I initially tested this on multiple boards there was some boards
that also hanged, that turned out to be an issue in one of the drivers.

If I remember correctly such hang was related to a null pointer
dereference or unaligned access in one of the drivers.

Could there be a similar underlying issue for these boards?

Regards,
Jonas

> 
> Fixes: 6d8cdfd1536 ("rockchip: spl: Enable caches to speed up checksum validation")
> 
> Signed-off-by: Simon Glass <sjg at chromium.org>
> ---
> 
>  configs/chromebook_bob_defconfig   | 1 +
>  configs/chromebook_kevin_defconfig | 1 +
>  2 files changed, 2 insertions(+)
> 
> diff --git a/configs/chromebook_bob_defconfig b/configs/chromebook_bob_defconfig
> index acfe3934104..b2ecfa6050c 100644
> --- a/configs/chromebook_bob_defconfig
> +++ b/configs/chromebook_bob_defconfig
> @@ -1,5 +1,6 @@
>  CONFIG_ARM=y
>  CONFIG_SKIP_LOWLEVEL_INIT=y
> +CONFIG_SPL_SYS_DCACHE_OFF=y
>  CONFIG_COUNTER_FREQUENCY=24000000
>  CONFIG_ARCH_ROCKCHIP=y
>  CONFIG_TEXT_BASE=0x00200000
> diff --git a/configs/chromebook_kevin_defconfig b/configs/chromebook_kevin_defconfig
> index 95fdb418d82..da748e4f022 100644
> --- a/configs/chromebook_kevin_defconfig
> +++ b/configs/chromebook_kevin_defconfig
> @@ -2,6 +2,7 @@ CONFIG_ARM=y
>  CONFIG_SKIP_LOWLEVEL_INIT=y
>  CONFIG_COUNTER_FREQUENCY=24000000
>  CONFIG_ARCH_ROCKCHIP=y
> +CONFIG_SPL_SYS_DCACHE_OFF=y
>  CONFIG_TEXT_BASE=0x00200000
>  CONFIG_SPL_GPIO=y
>  CONFIG_NR_DRAM_BANKS=1