[PATCH v4 01/10] arm64: dts: rockchip: Add rk3588 GPU node

[Kever Yang]

On 2024/5/29 01:03, Jianfeng Liu wrote:
> From: Boris Brezillon <boris.brezillon at collabora.com>
>
> Add Mali GPU Node to the RK3588 SoC DT including GPU clock
> operating points
>
> Signed-off-by: Boris Brezillon <boris.brezillon at collabora.com>
> Signed-off-by: Sebastian Reichel <sebastian.reichel at collabora.com>
> Link: https://lore.kernel.org/r/20240326165232.73585-3-sebastian.reichel@collabora.com
> Signed-off-by: Heiko Stuebner <heiko at sntech.de>
>
> [ upstream commit: 6fca4edb93d335f29f81e484936f38a5eed6a9b1 ]
>
> (cherry picked from commit 3cd15354ea0c8668812bc0b3a4136606c10803e9)
> Signed-off-by: Jianfeng Liu <liujianfeng1994 at gmail.com>
Reviewed-by: Kever Yang <kever.yang at rock-chips.com>

Thanks,
- Kever
> ---
>
> (no changes since v1)
>
>   dts/upstream/src/arm64/rockchip/rk3588s.dtsi | 56 ++++++++++++++++++++
>   1 file changed, 56 insertions(+)
>
> diff --git a/dts/upstream/src/arm64/rockchip/rk3588s.dtsi b/dts/upstream/src/arm64/rockchip/rk3588s.dtsi
> index 87b83c87bd5..89d40cff635 100644
> --- a/dts/upstream/src/arm64/rockchip/rk3588s.dtsi
> +++ b/dts/upstream/src/arm64/rockchip/rk3588s.dtsi
> @@ -501,6 +501,62 @@
>   		status = "disabled";
>   	};
>   
> +	gpu: gpu at fb000000 {
> +		compatible = "rockchip,rk3588-mali", "arm,mali-valhall-csf";
> +		reg = <0x0 0xfb000000 0x0 0x200000>;
> +		#cooling-cells = <2>;
> +		assigned-clocks = <&scmi_clk SCMI_CLK_GPU>;
> +		assigned-clock-rates = <200000000>;
> +		clocks = <&cru CLK_GPU>, <&cru CLK_GPU_COREGROUP>,
> +			 <&cru CLK_GPU_STACKS>;
> +		clock-names = "core", "coregroup", "stacks";
> +		dynamic-power-coefficient = <2982>;
> +		interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH 0>,
> +			     <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH 0>,
> +			     <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH 0>;
> +		interrupt-names = "job", "mmu", "gpu";
> +		operating-points-v2 = <&gpu_opp_table>;
> +		power-domains = <&power RK3588_PD_GPU>;
> +		status = "disabled";
> +
> +		gpu_opp_table: opp-table {
> +			compatible = "operating-points-v2";
> +
> +			opp-300000000 {
> +				opp-hz = /bits/ 64 <300000000>;
> +				opp-microvolt = <675000 675000 850000>;
> +			};
> +			opp-400000000 {
> +				opp-hz = /bits/ 64 <400000000>;
> +				opp-microvolt = <675000 675000 850000>;
> +			};
> +			opp-500000000 {
> +				opp-hz = /bits/ 64 <500000000>;
> +				opp-microvolt = <675000 675000 850000>;
> +			};
> +			opp-600000000 {
> +				opp-hz = /bits/ 64 <600000000>;
> +				opp-microvolt = <675000 675000 850000>;
> +			};
> +			opp-700000000 {
> +				opp-hz = /bits/ 64 <700000000>;
> +				opp-microvolt = <700000 700000 850000>;
> +			};
> +			opp-800000000 {
> +				opp-hz = /bits/ 64 <800000000>;
> +				opp-microvolt = <750000 750000 850000>;
> +			};
> +			opp-900000000 {
> +				opp-hz = /bits/ 64 <900000000>;
> +				opp-microvolt = <800000 800000 850000>;
> +			};
> +			opp-1000000000 {
> +				opp-hz = /bits/ 64 <1000000000>;
> +				opp-microvolt = <850000 850000 850000>;
> +			};
> +		};
> +	};
> +
>   	pmu1grf: syscon at fd58a000 {
>   		compatible = "rockchip,rk3588-pmugrf", "syscon", "simple-mfd";
>   		reg = <0x0 0xfd58a000 0x0 0x10000>;