[PATCH] arm: dts: corstone1000: enable secondary cores for FVP
harsimransingh.tungal at arm.com
harsimransingh.tungal at arm.com
Wed Jun 12 12:04:21 CEST 2024
From: Harsimran Singh Tungal <harsimransingh.tungal at arm.com>
Add the secondary cores nodes in the dts file
Signed-off-by: Harsimran Singh Tungal <harsimransingh.tungal at arm.com>
Cc: Tom Rini <trini at konsulko.com>
Cc: Rui Miguel Silva <rui.silva at linaro.org>
---
arch/arm/dts/corstone1000-fvp.dts | 25 +++++++++++++++++++++++++
arch/arm/dts/corstone1000.dtsi | 2 +-
2 files changed, 26 insertions(+), 1 deletion(-)
diff --git a/arch/arm/dts/corstone1000-fvp.dts b/arch/arm/dts/corstone1000-fvp.dts
index 26b0f1b3ce..3076fb9f34 100644
--- a/arch/arm/dts/corstone1000-fvp.dts
+++ b/arch/arm/dts/corstone1000-fvp.dts
@@ -49,3 +49,28 @@
clock-names = "smclk", "apb_pclk";
};
};
+
+&cpus {
+ cpu1: cpu at 1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a35";
+ reg = <0x1>;
+ enable-method = "psci";
+ next-level-cache = <&L2_0>;
+ };
+ cpu2: cpu at 2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a35";
+ reg = <0x2>;
+ enable-method = "psci";
+ next-level-cache = <&L2_0>;
+ };
+ cpu3: cpu at 3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a35";
+ reg = <0x3>;
+ enable-method = "psci";
+ next-level-cache = <&L2_0>;
+ };
+};
+
diff --git a/arch/arm/dts/corstone1000.dtsi b/arch/arm/dts/corstone1000.dtsi
index 1e0ec075e4..5d9d95b21c 100644
--- a/arch/arm/dts/corstone1000.dtsi
+++ b/arch/arm/dts/corstone1000.dtsi
@@ -21,7 +21,7 @@
stdout-path = "serial0:115200n8";
};
- cpus {
+ cpus: cpus {
#address-cells = <1>;
#size-cells = <0>;
--
2.25.1
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