[PATCH v5 1/2] arm: mediatek: add mt8195 SOC support

Shengyu Qu wiagn233 at outlook.com
Thu Jun 20 18:02:25 CEST 2024


Hello,

What happened to this series? Has it been abandoned? Also, is it
possible to get memory size installed to the board dynamically?

Best regards,
Shengyu

在 2023/8/4 19:04, Macpaul Lin 写道:
> From: Fabien Parent <fparent at baylibre.com>
> 
> The MediaTek MT8195 is a ARM64-based SoC with a quad-core Cortex-A73 and
> a quad-core Cortex-A53. It is including UART, SPI, USB3.0 device and hosts,
> SD and MMC cards, UFS, PWM, I2C, I2S, S/PDIF, and several LPDDR3
> and LPDDR4 options.
> 
> Signed-off-by: Fabien Parent <fparent at baylibre.com>
> Signed-off-by: Macpaul Lin <macpaul.lin at mediatek.com>
> Reviewed-by: Simon Glass <sjg at chromium.org>
> ---
>   MAINTAINERS                            |   2 +
>   arch/arm/dts/mt8195.dtsi               | 370 +++++++++++++++++++++++++
>   arch/arm/mach-mediatek/Kconfig         |  13 +-
>   arch/arm/mach-mediatek/Makefile        |   1 +
>   arch/arm/mach-mediatek/mt8195/Kconfig  |  13 +
>   arch/arm/mach-mediatek/mt8195/Makefile |   3 +
>   arch/arm/mach-mediatek/mt8195/init.c   |  97 +++++++
>   7 files changed, 498 insertions(+), 1 deletion(-)
>   create mode 100644 arch/arm/dts/mt8195.dtsi
>   create mode 100644 arch/arm/mach-mediatek/mt8195/Kconfig
>   create mode 100644 arch/arm/mach-mediatek/mt8195/Makefile
>   create mode 100644 arch/arm/mach-mediatek/mt8195/init.c
> 
> Changes for v2:
>   - Correct node name to t-phy for u3phy0.
>   - Add platform compatible string "mediatek,mt8195-tphy" to all usb phy nodes.
>   - remove clock nodes that software cannot controlled in phy nodes.
>   - Test and add back "mac" for HOST only xhci nodes.
> 
> Changes for v3:
>   - Revise device node name from "xhciX: xhciX@" to "xhciX: xhci@".
> 
> Changes for v4:
>   - No change.
> 
> Changes for v5:
>   - Fix Copyright year to 2023.
>   - Fix memory map in dram_init() to support 8GB onboard memory.
>   - Add '#if !IS_ENABLED(CONFIG_SYSRESET)' with reset_cpu().
>   - Correct reset_cpu() function prototype.
>   - rebase patchset to v2023-10.rc1
>   - Add missing arch/arm/mach-mediatek/mt8195/Kconfig.
> 
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 47581cf6fb..4d0f017e7e 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -369,8 +369,10 @@ ARM MEDIATEK
>   M:	Ryder Lee <ryder.lee at mediatek.com>
>   M:	Weijie Gao <weijie.gao at mediatek.com>
>   M:	Chunfeng Yun <chunfeng.yun at mediatek.com>
> +M:	Macpaul Lin <macpaul.lin at mediatek.com>
>   R:	GSS_MTK_Uboot_upstream <GSS_MTK_Uboot_upstream at mediatek.com>
>   S:	Maintained
> +F:	arch/arm/dts/mt8195.dtsi
>   F:	arch/arm/mach-mediatek/
>   F:	arch/arm/include/asm/arch-mediatek/
>   F:	board/mediatek/
> diff --git a/arch/arm/dts/mt8195.dtsi b/arch/arm/dts/mt8195.dtsi
> new file mode 100644
> index 0000000000..14cb28d008
> --- /dev/null
> +++ b/arch/arm/dts/mt8195.dtsi
> @@ -0,0 +1,370 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +/*
> + * Copyright (C) 2023 MediaTek Inc.
> + * Copyright (C) 2023 BayLibre, SAS
> + * Author: Ben Ho <ben.ho at mediatek.com>
> + *         Erin Lo <erin.lo at mediatek.com>
> + *         Fabien Parent <fparent at baylibre.com>
> + *         Macpaul Lin <macpaul.lin at mediatek.com>
> + */
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/phy/phy.h>
> +
> +/ {
> +	compatible = "mediatek,mt8195";
> +	interrupt-parent = <&sysirq>;
> +	#address-cells = <2>;
> +	#size-cells = <2>;
> +
> +	cpus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		cpu-map {
> +			cluster0 {
> +				core0 {
> +					cpu = <&cpu0>;
> +				};
> +				core1 {
> +					cpu = <&cpu1>;
> +				};
> +				core2 {
> +					cpu = <&cpu2>;
> +				};
> +				core3 {
> +					cpu = <&cpu3>;
> +				};
> +			};
> +
> +			cluster1 {
> +				core0 {
> +					cpu = <&cpu4>;
> +				};
> +				core1 {
> +					cpu = <&cpu5>;
> +				};
> +				core2 {
> +					cpu = <&cpu6>;
> +				};
> +				core3 {
> +					cpu = <&cpu7>;
> +				};
> +			};
> +		};
> +
> +		cpu0: cpu at 0 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a53";
> +			reg = <0x000>;
> +			enable-method = "psci";
> +			capacity-dmips-mhz = <741>;
> +		};
> +
> +		cpu1: cpu at 1 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a53";
> +			reg = <0x001>;
> +			enable-method = "psci";
> +			capacity-dmips-mhz = <741>;
> +		};
> +
> +		cpu2: cpu at 2 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a53";
> +			reg = <0x002>;
> +			enable-method = "psci";
> +			capacity-dmips-mhz = <741>;
> +		};
> +
> +		cpu3: cpu at 3 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a53";
> +			reg = <0x003>;
> +			enable-method = "psci";
> +			capacity-dmips-mhz = <741>;
> +		};
> +
> +		cpu4: cpu at 100 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a73";
> +			reg = <0x100>;
> +			enable-method = "psci";
> +			capacity-dmips-mhz = <1024>;
> +		};
> +
> +		cpu5: cpu at 101 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a73";
> +			reg = <0x101>;
> +			enable-method = "psci";
> +			capacity-dmips-mhz = <1024>;
> +		};
> +
> +		cpu6: cpu at 102 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a73";
> +			reg = <0x102>;
> +			enable-method = "psci";
> +			capacity-dmips-mhz = <1024>;
> +		};
> +
> +		cpu7: cpu at 103 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a73";
> +			reg = <0x103>;
> +			enable-method = "psci";
> +			capacity-dmips-mhz = <1024>;
> +		};
> +	};
> +
> +	clk26m: oscillator {
> +		compatible = "fixed-clock";
> +		#clock-cells = <0>;
> +		clock-frequency = <26000000>;
> +		clock-output-names = "clk26m";
> +	};
> +
> +	mmc_source_clk: mmc-source-clk{
> +		compatible = "fixed-clock";
> +		#clock-cells = <0>;
> +		clock-frequency = <400000000>;
> +		clock-output-names = "mmc_source_clk";
> +	};
> +
> +	soc {
> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +		compatible = "simple-bus";
> +		ranges;
> +
> +		watchdog: watchdog at 10007000 {
> +			compatible = "mediatek,mt8195-wdt",
> +				      "mediatek,wdt";
> +			reg = <0 0x10007000 0 0x100>;
> +			status = "disabled";
> +		};
> +
> +		gic: interrupt-controller at c000000 {
> +			compatible = "arm,gic-v3";
> +			#interrupt-cells = <4>;
> +			interrupt-parent = <&gic>;
> +			interrupt-controller;
> +			reg = <0 0x0c000000 0 0x40000>,  /* GICD */
> +			      <0 0x0c100000 0 0x200000>, /* GICR */
> +			      <0 0x0c400000 0 0x2000>,   /* GICC */
> +			      <0 0x0c410000 0 0x1000>,   /* GICH */
> +			      <0 0x0c420000 0 0x2000>;   /* GICV */
> +
> +			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
> +			ppi-partitions {
> +				ppi_cluster0: interrupt-partition-0 {
> +					affinity = <&cpu0 &cpu1 &cpu2 &cpu3>;
> +				};
> +				ppi_cluster1: interrupt-partition-1 {
> +					affinity = <&cpu4 &cpu5 &cpu6 &cpu7>;
> +				};
> +			};
> +		};
> +
> +		sysirq: interrupt-controller at c530a80 {
> +			compatible = "mediatek,mt8195-sysirq",
> +				     "mediatek,mt6577-sysirq";
> +			interrupt-controller;
> +			#interrupt-cells = <3>;
> +			interrupt-parent = <&gic>;
> +			reg = <0 0x0c530a80 0 0x50>;
> +		};
> +
> +		topckgen: syscon at 10000000 {
> +			compatible = "mediatek,mt8195-topckgen", "syscon";
> +			reg = <0 0x10000000 0 0x1000>;
> +			#clock-cells = <1>;
> +		};
> +
> +		infracfg: syscon at 10001000 {
> +			compatible = "mediatek,mt8195-infracfg", "syscon";
> +			reg = <0 0x10001000 0 0x1000>;
> +			#clock-cells = <1>;
> +		};
> +
> +		apmixedsys: syscon at 1000c000 {
> +			compatible = "mediatek,mt8195-apmixedsys", "syscon";
> +			reg = <0 0x1000c000 0 0x1000>;
> +			#clock-cells = <1>;
> +		};
> +
> +		uart0: serial at 11001100 {
> +			compatible = "mediatek,mt8195-uart",
> +				     "mediatek,hsuart";
> +			reg = <0 0x11001100 0 0x1000>;
> +			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
> +			clock-frequency = <26000000>;
> +			clocks = <&clk26m>, <&clk26m>;
> +			clock-names = "baud", "bus";
> +			status = "disabled";
> +		};
> +
> +		mmc0: mmc at 11230000 {
> +			compatible = "mediatek,mt8195-mmc",
> +				     "mediatek,mt8183-mmc";
> +			reg = <0 0x11230000 0 0x1000>,
> +			      <0 0x11f50000 0 0x1000>;
> +			interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
> +			clocks = <&mmc_source_clk>,
> +				 <&clk26m>,
> +				 <&clk26m>;
> +			clock-names = "source", "hclk", "source_cg";
> +			status = "disabled";
> +		};
> +
> +		u3phy0: t-phy at 11f40000 {
> +			compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v2";
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			ranges = <0 0 0x11e40000 0xe00>;
> +			status = "okay";
> +
> +			u2port0: usb-phy at 0 {
> +				reg = <0 0x700>;
> +				#phy-cells = <1>;
> +				status = "okay";
> +			};
> +
> +			u3port0: usb-phy at 700 {
> +				reg = <0x700 0x700>;
> +				#phy-cells = <1>;
> +				status = "okay";
> +			};
> +		};
> +
> +		usb: usb at 11200000 {
> +			compatible ="mediatek,mt8195-mtu3", "mediatek,mtu3";
> +			reg = <0 0x11203e00 0 0x0100>;
> +			reg-names = "ippc";
> +			phys = <&u2port0 PHY_TYPE_USB2>;
> +			clocks = <&clk26m>,
> +				 <&clk26m>,
> +				 <&clk26m>;
> +			clock-names = "sys_ck", "ref_ck", "mcu_ck";
> +			#address-cells = <2>;
> +			#size-cells = <2>;
> +			ranges;
> +			status = "disabled";
> +
> +			ssusb: ssusb at 11200000 {
> +				compatible = "mediatek,ssusb";
> +				reg = <0 0x11200000 0 0x3e00>;
> +				reg-names = "mac";
> +				interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_LOW>;
> +				status = "disabled";
> +			};
> +
> +			xhci0: xhci at 11200000 {
> +				compatible = "mediatek,mtk-xhci";
> +				reg = <0 0x11200000 0 0x1000>;
> +				reg-names = "mac";
> +				interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_LOW>;
> +				clocks = <&clk26m>,
> +					 <&clk26m>,
> +					 <&clk26m>,
> +					 <&clk26m>;
> +				clock-names = "sys_ck", "xhci_ck", "ref_ck", "mcu_ck";
> +				status = "disabled";
> +			};
> +		};
> +
> +		u3phy1: t-phy at 11e30000 {
> +			compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v2";
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			ranges = <0 0 0x11e30000 0xe00>;
> +			status = "disabled";
> +
> +			u2port1: usb-phy at 0 {
> +				reg = <0x0 0x700>;
> +				#phy-cells = <1>;
> +			};
> +
> +			u3port1: usb-phy at 700 {
> +				reg = <0x700 0x700>;
> +				#phy-cells = <1>;
> +			};
> +		};
> +
> +		xhci1: xhci at 11290000 {
> +			compatible = "mediatek,mt8195-xhci",
> +				     "mediatek,mtk-xhci";
> +			reg = <0 0x11290000 0 0x1000>,
> +			      <0 0x11293e00 0 0x0100>;
> +			reg-names = "mac", "ippc";
> +			interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>;
> +			phys = <&u2port1 PHY_TYPE_USB2>;
> +			clocks = <&clk26m>,
> +				 <&clk26m>,
> +				 <&clk26m>,
> +				 <&clk26m>;
> +			clock-names = "sys_ck", "xhci_ck", "ref_ck", "mcu_ck";
> +			status = "disabled";
> +		};
> +
> +		u3phy2: t-phy at 11c40000 {
> +			compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v2";
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			ranges = <0 0 0x11c40000 0x700>;
> +			status = "disabled";
> +
> +			u2port2: usb-phy at 0 {
> +				reg = <0x0 0x700>;
> +				#phy-cells = <1>;
> +			};
> +		};
> +
> +		xhci2: xhci at 112a0000 {
> +			compatible = "mediatek,mt8195-xhci",
> +				     "mediatek,mtk-xhci";
> +			reg = <0 0x112a0000 0 0x1000>,
> +			      <0 0x112a3e00 0 0x0100>;
> +			reg-names = "mac", "ippc";
> +			interrupts = <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>;
> +			phys = <&u2port2 PHY_TYPE_USB2>;
> +			clocks = <&clk26m>,
> +				 <&clk26m>,
> +				 <&clk26m>;
> +			clock-names = "sys_ck", "xhci_ck", "ref_ck";
> +			status = "disabled";
> +		};
> +
> +		u3phy3: t-phy at 11c50000 {
> +			compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v2";
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			ranges = <0 0 0x11c50000 0x700>;
> +			status = "okay";
> +
> +			u2port3: usb-phy at 0 {
> +				reg = <0x0 0x700>;
> +				#phy-cells = <1>;
> +			};
> +		};
> +
> +		xhci3: xhci at 112b0000 {
> +			compatible = "mediatek,mt8195-xhci",
> +				     "mediatek,mtk-xhci";
> +			reg = <0 0x112b0000 0 0x1000>,
> +			      <0 0x112b3e00 0 0x0100>;
> +			reg-names = "mac", "ippc";
> +			interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH>;
> +			phys = <&u2port3 PHY_TYPE_USB2>;
> +			clocks = <&clk26m>,
> +				 <&clk26m>,
> +				 <&clk26m>;
> +			clock-names = "sys_ck", "xhci_ck", "ref_ck";
> +			usb2-lpm-disable;
> +			status = "disabled";
> +		};
> +	};
> +};
> diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-mediatek/Kconfig
> index 04aa2fd97f..3a2af1cdee 100644
> --- a/arch/arm/mach-mediatek/Kconfig
> +++ b/arch/arm/mach-mediatek/Kconfig
> @@ -67,6 +67,15 @@ config TARGET_MT8183
>   	  SD and MMC cards, UFS, PWM, I2C, I2S, S/PDIF, and several LPDDR3
>   	  and LPDDR4 options.
>   
> +config TARGET_MT8195
> +	bool "MediaTek MT8195 SoC"
> +	select ARM64
> +	help
> +	  The MediaTek MT8195 is a ARM64-based SoC with a quad-core Cortex-A73 and
> +	  a quad-core Cortex-A53. It is including UART, SPI, USB3.0 device and hosts,
> +	  SD and MMC cards, UFS, PWM, I2C, I2S, S/PDIF, and several LPDDR3
> +	  and LPDDR4 options.
> +
>   config TARGET_MT8512
>           bool "MediaTek MT8512 M1 Board"
>           select ARM64
> @@ -105,6 +114,7 @@ config SYS_BOARD
>   	default "mt7981" if TARGET_MT7981
>   	default "mt7986" if TARGET_MT7986
>   	default "mt8183" if TARGET_MT8183
> +	default "mt8195" if TARGET_MT8195
>   	default "mt8512" if TARGET_MT8512
>   	default "mt8516" if TARGET_MT8516
>   	default "mt8518" if TARGET_MT8518
> @@ -122,6 +132,7 @@ config SYS_CONFIG_NAME
>   	default "mt7981" if TARGET_MT7981
>   	default "mt7986" if TARGET_MT7986
>   	default "mt8183" if TARGET_MT8183
> +	default "mt8195" if TARGET_MT8195
>   	default "mt8512" if TARGET_MT8512
>   	default "mt8516" if TARGET_MT8516
>   	default "mt8518" if TARGET_MT8518
> @@ -134,7 +145,7 @@ config SYS_CONFIG_NAME
>   config MTK_BROM_HEADER_INFO
>   	string
>   	default "media=nor" if TARGET_MT8518 || TARGET_MT8512 || TARGET_MT7629 || TARGET_MT7622
> -	default "media=emmc" if TARGET_MT8516 || TARGET_MT8365 || TARGET_MT8183
> +	default "media=emmc" if TARGET_MT8516 || TARGET_MT8365 || TARGET_MT8183 || TARGET_MT8195
>   	default "media=snand;nandinfo=2k+64" if TARGET_MT7981 || TARGET_MT7986
>   	default "lk=1" if TARGET_MT7623
>   
> diff --git a/arch/arm/mach-mediatek/Makefile b/arch/arm/mach-mediatek/Makefile
> index fc85293f71..fbbb5431d1 100644
> --- a/arch/arm/mach-mediatek/Makefile
> +++ b/arch/arm/mach-mediatek/Makefile
> @@ -10,5 +10,6 @@ obj-$(CONFIG_TARGET_MT7629) += mt7629/
>   obj-$(CONFIG_TARGET_MT7981) += mt7981/
>   obj-$(CONFIG_TARGET_MT7986) += mt7986/
>   obj-$(CONFIG_TARGET_MT8183) += mt8183/
> +obj-$(CONFIG_TARGET_MT8195) += mt8195/
>   obj-$(CONFIG_TARGET_MT8516) += mt8516/
>   obj-$(CONFIG_TARGET_MT8518) += mt8518/
> diff --git a/arch/arm/mach-mediatek/mt8195/Kconfig b/arch/arm/mach-mediatek/mt8195/Kconfig
> new file mode 100644
> index 0000000000..a34fa2cf2e
> --- /dev/null
> +++ b/arch/arm/mach-mediatek/mt8195/Kconfig
> @@ -0,0 +1,13 @@
> +if TARGET_MT8195
> +
> +config SYS_BOARD
> +	default "mt8195"
> +
> +config SYS_CONFIG_NAME
> +	default "mt8195"
> +
> +config MTK_BROM_HEADER_INFO
> +	string
> +	default "media=emmc"
> +
> +endif
> diff --git a/arch/arm/mach-mediatek/mt8195/Makefile b/arch/arm/mach-mediatek/mt8195/Makefile
> new file mode 100644
> index 0000000000..886ab7e4eb
> --- /dev/null
> +++ b/arch/arm/mach-mediatek/mt8195/Makefile
> @@ -0,0 +1,3 @@
> +# SPDX-License-Identifier:	GPL-2.0
> +
> +obj-y += init.o
> diff --git a/arch/arm/mach-mediatek/mt8195/init.c b/arch/arm/mach-mediatek/mt8195/init.c
> new file mode 100644
> index 0000000000..8d6b700e7e
> --- /dev/null
> +++ b/arch/arm/mach-mediatek/mt8195/init.c
> @@ -0,0 +1,97 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2023 MediaTek Inc.
> + * Copyright (C) 2023 BayLibre, SAS
> + * Author: Macpaul Lin <macpaul.lin at mediatek.com>
> + * Author: Fabien Parent <fparent at baylibre.com>
> + */
> +
> +#include <clk.h>
> +#include <common.h>
> +#include <cpu_func.h>
> +#include <dm.h>
> +#include <fdtdec.h>
> +#include <ram.h>
> +#include <asm/arch/misc.h>
> +#include <asm/armv8/mmu.h>
> +#include <asm/sections.h>
> +#include <asm/system.h>
> +#include <dm/uclass.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +int dram_init(void)
> +{
> +	int ret;
> +
> +	ret = fdtdec_setup_memory_banksize();
> +	if (ret)
> +		return ret;
> +
> +	fdtdec_setup_mem_size_base();
> +
> +	/*
> +	 * Limit gd->ram_top not exceeding SZ_4G.
> +	 * Because some periphals like mmc requires DMA buffer
> +	 * allocaed below SZ_4G.
> +	 *
> +	 * Note: SZ_2M is for adjusting gd->relocaddr,
> +	 *       the reserved memory for u-boot itself.
> +	 */
> +	if (gd->ram_base + gd->ram_size >= SZ_4G)
> +		gd->mon_len = SZ_4G + gd->ram_base + SZ_2M;
> +
> +	return 0;
> +}
> +
> +int dram_init_banksize(void)
> +{
> +	gd->bd->bi_dram[0].start = gd->ram_base;
> +	gd->bd->bi_dram[0].size = gd->ram_size;
> +
> +	return 0;
> +}
> +
> +int mtk_pll_early_init(void)
> +{
> +	return 0;
> +}
> +
> +int mtk_soc_early_init(void)
> +{
> +	return 0;
> +}
> +
> +#if !IS_ENABLED(CONFIG_SYSRESET)
> +void reset_cpu(void)
> +{
> +	psci_system_reset();
> +}
> +#endif
> +
> +int print_cpuinfo(void)
> +{
> +	printf("CPU:   MediaTek MT8195\n");
> +	return 0;
> +}
> +
> +static struct mm_region mt8195_mem_map[] = {
> +	{
> +		/* DDR */
> +		.virt = 0x40000000UL,
> +		.phys = 0x40000000UL,
> +		.size = 0x200000000UL,
> +		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE,
> +	}, {
> +		.virt = 0x00000000UL,
> +		.phys = 0x00000000UL,
> +		.size = 0x20000000UL,
> +		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
> +			 PTE_BLOCK_NON_SHARE |
> +			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
> +	}, {
> +		0,
> +	}
> +};
> +
> +struct mm_region *mem_map = mt8195_mem_map;
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