[PATCH v2 1/1] net: ti: am65-cpsw-nuss: Remove incorrect RGMII_ID bit functionality

[Tom Rini]

On Thu, Feb 01, 2024 at 08:17:05PM +0000, Ken Sloat wrote:

> The CPSW implementations on the AM6x platforms do not support the
> selectable RGMII TX clk delay functionality via the RGMII_ID_MODE bit as
> the earlier platforms did. While it is possible to write the bit,
> according to various TI AM6x datasheets, reference manuals, hardware
> design guides and TI forum posts from TI, this bit is "not timed, tested
> or characterized. RGMII_ID is enabled by default."
> 
> The driver implementation today however, will incorrectly set this bit
> whenever the interface mode is in RGMII_ID or RGMII_TXID. Since
> disabling the delay (bit=1) is not supported by TI, this bit should
> always be written as 0.
> 
> See:
> https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1211306/am625-enet1_ctrl_rgmii_id-_mode
> https://www.ti.com/lit/pdf/spruiv7 (Rev. B Figure 14-1717)
> https://www.ti.com/lit/gpn/am625 (Rev. B Figure 7-31 Note A)
> https://www.ti.com/lit/an/sprad05b/sprad05b.pdf (Rev. B Section 7.4)
> 
> Signed-off-by: Ken Sloat <ken.s at variscite.com>
> Reviewed-by: Roger Quadros <rogerq at kernel.org>

The whitespace in this version was totally destroyed, please re-send,
thanks.

-- 
Tom
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