[PATCH] clk/qcom: apq8016: allow apq8016_clk_init_uart() to be called externally
Caleb Connolly
caleb.connolly at linaro.org
Fri Mar 1 16:00:24 CET 2024
When U-Boot as running as the first stage bootloader on MSM8916 devices,
early debug UART requires turning on the clocks (for some reason the
pre-loader turns them off?!).
To simplify developing for this platform, allow the
apq8016_clk_init_uart() function to be called externally. Developers can
call this from the serial_msm debug uart driver to configure the clocks
before the driver model is available.
As it is only possible to enable early debug UART in custom builds of
U-Boot, this solution at least gives developers the option.
Signed-off-by: Caleb Connolly <caleb.connolly at linaro.org>
---
This patch was meant to be in v5 of my Qualcomm generic board support series[1],
but got lost somewhere in the mix.
[1]: https://lore.kernel.org/u-boot/CAFA6WYNXE3x8sKRB8BBpODCfXbZeeVpKPu0-qt7ezsY-R7unQQ@mail.gmail.com/
---
drivers/clk/qcom/clock-apq8016.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/clk/qcom/clock-apq8016.c b/drivers/clk/qcom/clock-apq8016.c
index 9de0ad5ed32d..e6647f7c41dd 100644
--- a/drivers/clk/qcom/clock-apq8016.c
+++ b/drivers/clk/qcom/clock-apq8016.c
@@ -102,22 +102,22 @@ static const struct bcr_regs uart2_regs = {
.D = BLSP1_UART2_APPS_D,
};
/* UART: 115200 */
-static int clk_init_uart(struct msm_clk_priv *priv)
+int apq8016_clk_init_uart(phys_addr_t base)
{
/* Enable AHB clock */
- clk_enable_vote_clk(priv->base, &gcc_blsp1_ahb_clk);
+ clk_enable_vote_clk(base, &gcc_blsp1_ahb_clk);
/* 7372800 uart block clock @ GPLL0 */
- clk_rcg_set_rate_mnd(priv->base, &uart2_regs, 1, 144, 15625,
+ clk_rcg_set_rate_mnd(base, &uart2_regs, 1, 144, 15625,
CFG_CLK_SRC_GPLL0, 16);
/* Vote for gpll0 clock */
- clk_enable_gpll0(priv->base, &gpll0_vote_clk);
+ clk_enable_gpll0(base, &gpll0_vote_clk);
/* Enable core clk */
- clk_enable_cbc(priv->base + BLSP1_UART2_APPS_CBCR);
+ clk_enable_cbc(base + BLSP1_UART2_APPS_CBCR);
return 0;
}
@@ -132,9 +132,9 @@ static ulong apq8016_clk_set_rate(struct clk *clk, ulong rate)
case GCC_SDCC2_APPS_CLK: /* SDC2 */
return clk_init_sdc(priv, 1, rate);
break;
case GCC_BLSP1_UART2_APPS_CLK: /* UART2 */
- return clk_init_uart(priv);
+ return apq8016_clk_init_uart(priv->base);
break;
default:
return 0;
}
--
2.43.1
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