[PATCH 1/8] clk: qcom: clear div mask before assigning new divider

[Caleb Connolly]

On 29/02/2024 14:21, Volodymyr Babchuk wrote:
> We need to do this to ensure that new divider is applied
"The current behaviour does a bitwise OR of the previous and new divider
values, this is wrong."
> correctly. This fixes potential issue with 1Gbit ethernet on
> SA8155P-ADP boards.

Wow, that's a subtle one!
> 
> Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk at epam.com>
Small nit with the wording, otherwise

Reviewed-by: Caleb Connolly <caleb.connolly at linaro.org>
> ---
> 
>  drivers/clk/qcom/clock-qcom.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/qcom/clock-qcom.c b/drivers/clk/qcom/clock-qcom.c
> index 7c683e5192..729d190c54 100644
> --- a/drivers/clk/qcom/clock-qcom.c
> +++ b/drivers/clk/qcom/clock-qcom.c
> @@ -117,7 +117,8 @@ void clk_rcg_set_rate_mnd(phys_addr_t base, const struct bcr_regs *regs,
>  
>  	/* setup src select and divider */
>  	cfg  = readl(base + regs->cfg_rcgr);
> -	cfg &= ~(CFG_SRC_SEL_MASK | CFG_MODE_MASK | CFG_HW_CLK_CTRL_MASK);
> +	cfg &= ~(CFG_SRC_SEL_MASK | CFG_MODE_MASK | CFG_HW_CLK_CTRL_MASK |
> +		 CFG_SRC_DIV_MASK);
>  	cfg |= source & CFG_SRC_SEL_MASK; /* Select clock source */
>  
>  	if (div)

-- 
// Caleb (they/them)