[PATCH v2 2/2] riscv: cache: Implement dcache for cv1800b
Leo Liang
ycliang at andestech.com
Tue Mar 12 10:44:19 CET 2024
On Sun, Mar 10, 2024 at 12:54:57AM +0800, Kongyang Liu wrote:
> Add dcache operations invalidate_dcache_range and flush_dcache_range for
> cv1800b.
>
> Signed-off-by: Kongyang Liu <seashell11234455 at gmail.com>
> ---
>
> (no changes since v1)
>
> arch/riscv/cpu/cv1800b/Makefile | 1 +
> arch/riscv/cpu/cv1800b/cache.c | 45 +++++++++++++++++++++++++++++++++
> 2 files changed, 46 insertions(+)
> create mode 100644 arch/riscv/cpu/cv1800b/cache.c
Reviewed-by: Leo Yu-Chi Liang <ycliang at andestech.com>
More information about the U-Boot
mailing list