[PATCH 4/4] mtd: nand: raw: atmel: Introduce optional debug commands

[Mihai.Sain at microchip.com]

Hi Alexander,

>       Maybe we should add an automatic fallback for timing mode in nand-controller.c 😊
>       As of now the driver is forcing tRC_min to 30ns (mode 3), which is not reliable for sama7 nfc controller ☹
>       https://github.com/u-boot/u-boot/blob/master/drivers/mtd/nand/raw/nand_timings.c#L167
>       The nand torture command helped me to manually force tRC_min to 35ns (mode 2).

This sounds like the same problem encountered in
https://github.com/linux4sam/at91bootstrap/issues/174 and the fix proposed there works in Linux and U-Boot as well.  I consider the original commit message of the patch attached to that ticket not easy to understand however, so I wrote what I think is the problem.  Could you please test the patch attached to this mail which does the same thing and should apply to U-Boot cleanly?  I tested that on sam9x60 and sama5, but have no other boards/socs to test with.  If that works on sama7, I will propose it on U-Boot, too.

(I hope it is okay to attach it as an attachment for now, it's not ready for submission anyways.)

	I tested your patch on sama7g54-curiosity board.
	I also reverted to (conf->timings.sdr.tRC_min < 30000), to force mode 3 😊
	Indeed the decode command reports tighter timings.
	I tested using nand torture on 16MiB and 32MiB sizes.

U-Boot> nand info

Device 0: nand0, sector size 256 KiB
  Manufacturer  MACRONIX
  Model         MX30LF4G28AD
  Device size        512 MiB
  Page size         4096 b
  OOB size           256 b
  Erase size      262144 b
  ecc strength         8 bits
  ecc step size      512 b
  subpagesize       4096 b
  options       0x40004200
  bbt options   0x00028000

U-Boot> hsmc decode

mck clock rate: 200000000

HSMC_SETUP3:    0x00000002
HSMC_PULSE3:    0x07040703
HSMC_CYCLE3:    0x00070007
HSMC_TIMINGS3:  0x880402f2
HSMC_MODE3:     0x001f0003
NCS_RD: setup: 0 (0 ns), pulse: 7 (35 ns), hold: 0 (0 ns), cycle: 7 (35 ns)
   NRD: setup: 0 (0 ns), pulse: 4 (20 ns), hold: 3 (15 ns), cycle: 7 (35 ns)
NCS_WR: setup: 0 (0 ns), pulse: 7 (35 ns), hold: 0 (0 ns), cycle: 7 (35 ns)
   NWE: setup: 2 (10 ns), pulse: 3 (15 ns), hold: 2 (10 ns), cycle: 7 (35 ns)
TDF optimization enabled
TDF cycles: 15 (75 ns)
Data Bus Width: 8-bit bus
NWAIT Mode: 0
Write operation controlled by NWE signal
Read operation controlled by NRD signal

U-Boot> nand torture 0x800000 0x1000000

NAND torture: device 0 offset 0x800000 size 0x1000000 (block size 0x40000)
 Passed: 64, failed: 0

U-Boot> nand torture 0x800000 0x2000000

NAND torture: device 0 offset 0x800000 size 0x2000000 (block size 0x40000)
 Passed: 128, failed: 0

Tested-by: Mihai Sain <mihai.sain at microchip.com>

Best regards,
Mihai Sain